公开(公告)号：US20190103067A1

公开(公告)日：2019-04-04

申请号：US15723958

申请日：2017-10-03

Applicant: LG Display Co., Ltd.

Inventor： Yeonkyung KIM ,  Taewoong MOON ,  Junghyun LEE

IPC: G09G3/36 ,  G09G3/20 ,  G09G3/3266 ,  G06F3/041 ,  G11C19/28

Abstract: The present disclosure relates to a gate driving circuit and a display device using the circuit. A gate driving circuit according to an aspect of the present disclosure comprises a Q node controller, a QB node controller, and an output unit generating a pulse-type output signal by controlling charging and discharging of an output terminal according to the voltages of the Q node and the QB node, and the QB node controller controls the voltage of the QB node in an alternating manner during a non-scan period in which the Q node controller outputs a low level voltage for the Q node.

公开(公告)号：US20180121023A1

公开(公告)日：2018-05-03

申请号：US15798011

申请日：2017-10-30

Applicant: LG DISPLAY CO., LTD.

Inventor： Yeonkyung KIM ,  Taewoong MOON ,  Junghyun LEE

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/36

CPC classification number: G06F3/0418 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2300/0866 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2354/00

Abstract: A gate driver and a display device having an in-cell touch sensor using the gate driver are disclosed. The gate driver includes a shift register configured to sequentially supply gate pulses to gate lines of a display panel. The shift register includes an (N−1)th stage, where N is a positive integer equal to or greater than 2, configured to output an (N−1)th gate pulse, an Nth stage configured to output an Nth gate pulse, and a hold circuit configured to hold an output voltage of the (N−1)th stage during a predetermined time and supply the output voltage to the Nth stage.

公开(公告)号：US20180096645A1

公开(公告)日：2018-04-05

申请号：US15720869

申请日：2017-09-29

Applicant: LG DISPLAY CO., LTD.

Inventor： Junghyun LEE ,  Taewoong MOON ,  Yeonkyung KIM

IPC: G09G3/20

Abstract: A gate drive circuit and a display device are provided. The gate drive circuit comprises: a first stage that outputs a first gate pulse at a first output terminal by increasing a voltage at the first output terminal when a first Q node is charged in response to receiving a first carry signal at a first start terminal, and decreasing the voltage at the first output terminal when a first QB node is charged; and a second stage that outputs a second gate pulse at a second output terminal and outputs a second carry signal at a third output terminal by increasing voltages at the second and third output terminals when a second Q node is charged in response to receiving the first carry signal at a second start terminal, and decreasing the voltages at the second and third output terminals when a second QB node is charged.