GLASS PATTERNED RETARDER STEREOSCOPIC 3D DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME
    1.
    发明申请
    GLASS PATTERNED RETARDER STEREOSCOPIC 3D DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME 有权
    玻璃图形延迟器立体3D显示装置及其制造方法

    公开(公告)号:US20130135723A1

    公开(公告)日:2013-05-30

    申请号:US13682427

    申请日:2012-11-20

    CPC classification number: G02B27/26 Y10T29/49885

    Abstract: Discussed are a glass patterned retarder stereoscopic 3D display device and a method for fabricating the same. The device is capable of enhancing a viewing angle in upper and lower directions and an aperture ratio by forming light shielding patterns on a rear surface of a color filter substrate. Further, the device is capable of preventing scratches occurring on the light shielding patterns due to a polishing belt, by forming high hardness polymer on the light shielding patterns and removing stair-steps of a rear indium tin oxide (ITO).

    Abstract translation: 讨论了玻璃图案化延迟器立体3D显示装置及其制造方法。 该装置能够通过在滤色器基板的后表面上形成遮光图案来增强上下方向的视角和开口率。 此外,该装置能够通过在遮光图案上形成高硬度聚合物并去除后氧化铟锡(ITO)的台阶,能够防止由于抛光带在遮光图案上产生划痕。

    GATE DRIVING CIRCUIT AND DISPLAY DEVICE USING THE SAME

    公开(公告)号:US20190103067A1

    公开(公告)日:2019-04-04

    申请号:US15723958

    申请日:2017-10-03

    Abstract: The present disclosure relates to a gate driving circuit and a display device using the circuit. A gate driving circuit according to an aspect of the present disclosure comprises a Q node controller, a QB node controller, and an output unit generating a pulse-type output signal by controlling charging and discharging of an output terminal according to the voltages of the Q node and the QB node, and the QB node controller controls the voltage of the QB node in an alternating manner during a non-scan period in which the Q node controller outputs a low level voltage for the Q node.

    GATE DRIVE CIRCUIT AND DISPLAY DEVICE USING THE SAME

    公开(公告)号:US20180096645A1

    公开(公告)日:2018-04-05

    申请号:US15720869

    申请日:2017-09-29

    Abstract: A gate drive circuit and a display device are provided. The gate drive circuit comprises: a first stage that outputs a first gate pulse at a first output terminal by increasing a voltage at the first output terminal when a first Q node is charged in response to receiving a first carry signal at a first start terminal, and decreasing the voltage at the first output terminal when a first QB node is charged; and a second stage that outputs a second gate pulse at a second output terminal and outputs a second carry signal at a third output terminal by increasing voltages at the second and third output terminals when a second Q node is charged in response to receiving the first carry signal at a second start terminal, and decreasing the voltages at the second and third output terminals when a second QB node is charged.

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