Abstract:
Discussed are a glass patterned retarder stereoscopic 3D display device and a method for fabricating the same. The device is capable of enhancing a viewing angle in upper and lower directions and an aperture ratio by forming light shielding patterns on a rear surface of a color filter substrate. Further, the device is capable of preventing scratches occurring on the light shielding patterns due to a polishing belt, by forming high hardness polymer on the light shielding patterns and removing stair-steps of a rear indium tin oxide (ITO).
Abstract:
The present disclosure relates to a gate driving circuit and a display device using the circuit. A gate driving circuit according to an aspect of the present disclosure comprises a Q node controller, a QB node controller, and an output unit generating a pulse-type output signal by controlling charging and discharging of an output terminal according to the voltages of the Q node and the QB node, and the QB node controller controls the voltage of the QB node in an alternating manner during a non-scan period in which the Q node controller outputs a low level voltage for the Q node.
Abstract:
A gate driver and a display device having an in-cell touch sensor using the gate driver are disclosed. The gate driver includes a shift register configured to sequentially supply gate pulses to gate lines of a display panel. The shift register includes an (N−1)th stage, where N is a positive integer equal to or greater than 2, configured to output an (N−1)th gate pulse, an Nth stage configured to output an Nth gate pulse, and a hold circuit configured to hold an output voltage of the (N−1)th stage during a predetermined time and supply the output voltage to the Nth stage.
Abstract:
A gate drive circuit and a display device are provided. The gate drive circuit comprises: a first stage that outputs a first gate pulse at a first output terminal by increasing a voltage at the first output terminal when a first Q node is charged in response to receiving a first carry signal at a first start terminal, and decreasing the voltage at the first output terminal when a first QB node is charged; and a second stage that outputs a second gate pulse at a second output terminal and outputs a second carry signal at a third output terminal by increasing voltages at the second and third output terminals when a second Q node is charged in response to receiving the first carry signal at a second start terminal, and decreasing the voltages at the second and third output terminals when a second QB node is charged.