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    Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
    3.
    发明授权
    Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test 有权
    多捕获DFT系统，用于在自检或扫描测试期间检测或定位跨时钟域故障

    公开(公告)号：US07779323B2

    公开(公告)日：2010-08-17

    申请号：US12222931

    申请日：2008-08-20

    申请人： Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Hsin-Po Wang ,  Hao-Jan Chao ,  Xiaoqing Wen

    发明人： Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Hsin-Po Wang ,  Hao-Jan Chao ,  Xiaoqing Wen

    IPC分类号： G01R31/28 ,  G06F11/00

    CPC分类号： G06F17/5022 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594 ,  G06F17/5031 ,  G06F17/505

    摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

    摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的故障，以及跨越自检或扫描测试模式的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1且每个域具有 多个扫描单元。 该方法和装置允许在移位操作期间将N个伪随机数或预定刺激生成并加载到集成电路或电路组件中的N个时钟域内的所有扫描单元，向N中的所有扫描单元应用捕获时钟的有序序列 捕获操作期间的时钟域，压缩或比较所有扫描单元的N个输出响应，以便在紧凑/比较操作期间进行分析，并重复上述处理，直到达到预定的限制标准。 进一步开发了计算机辅助设计（CAD）系统来实现该方法并综合了该装置。

    Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
    4.
    发明授权
    Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits 失效
    用于基于扫描的集成电路的调试，诊断和产量改进的方法和装置

    公开(公告)号：US07058869B2

    公开(公告)日：2006-06-06

    申请号：US10762571

    申请日：2004-01-23

    申请人： Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Hao-Jan Chao ,  Hsin-Po Wang

    发明人： Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Hao-Jan Chao ,  Hsin-Po Wang

    IPC分类号： G01R31/3177 ,  G01R31/3181 ,  G01R31/3185

    CPC分类号： G01R31/318572 ,  G01R31/31705 ,  G01R31/318591

    摘要： A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations. Computer-aided design (CAD) methods are then proposed to automatically synthesize the output-mask controller 301, output-mask network 304, input chain-mask controller and input-mask network, and to further generate test patterns according to the synthesized scan-based integrated circuit.

    摘要翻译： 一种用于基于扫描的集成电路的调试，诊断和/或产量改进的方法和装置，其中嵌入在扫描核心303中的扫描链没有外部访问，例如当它们被图案发生器302和模式压缩器包围时的情况 305，使用DFT（设计为测试）技术，如Logic BIST（内置自检）或压缩扫描。 本发明包括一个输出屏蔽控制器301和一个输出屏蔽网络304，以允许设计者掩蔽所选择的扫描单元311在选定的模式压实器305中被压缩。 本发明还包括输入链掩模控制器和输入掩模网络，用于将恒定逻辑值驱动到所选扫描链的扫描链输入中，以允许设计者从扫描链保持时间违规恢复。 然后提出了计算机辅助设计（CAD）方法来自动合成输出掩模控制器301，输出掩模网络304，输入链掩模控制器和输入掩模网络，并根据合成的扫描 - 基于集成电路。

    Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
    5.
    发明授权
    Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques 有权
    使用设计调试（DFD）技术诊断集成电路故障的方法和装置

    公开(公告)号：US07191373B2

    公开(公告)日：2007-03-13

    申请号：US10086214

    申请日：2002-02-27

    申请人： Laung-Terng (L.-T.) Wang ,  Ming-Tung Chang ,  Shyh-Horng Lin ,  Hao-Jan Chao ,  Jaehee Lee ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Sen-Wei Tsai ,  Chi-Chan Hsu

    发明人： Laung-Terng (L.-T.) Wang ,  Ming-Tung Chang ,  Shyh-Horng Lin ,  Hao-Jan Chao ,  Jaehee Lee ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Sen-Wei Tsai ,  Chi-Chan Hsu

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3185 ,  G01R31/31704 ,  G01R31/31705

    摘要： A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

    摘要翻译： 一种用于在集成电路中插入设计调试（DFD）电路以调试或诊断DFT模块（包括扫描核心），存储器BIST（内置自检）内核，逻辑BIST核心和功能核心的方法和装置。 本发明还包括使用DFD控制器来执行多个DFD命令来调试或诊断嵌入在DFD电路中的DFT模块。 当单独使用或组合在一起时，这些DFD命令将使用低成本DFT调试器在评估板或系统上的集成电路中的DFT模块中检测或定位物理故障。 根据IEEE 1149.1边界扫描标准，进一步开发了一种计算机辅助设计（CAD）方法来合成DFD控制器和DFD电路。 DFD控制器支持但不限于以下DFD命令：RUN_SCAN，RUN_MBIST，RUN_LBIST，DBG_SCAN，DBG_MBIST，DBG_LBIST，DBG_FUNCTION，SELECT，SHIFT，SHIFT_CHAIN，CAPTURE，RESET，BREAK，RUN，STEP和STOP。

    Multiple-capture DFT system to reduce peak capture power during self-test or scan test
    8.
    发明授权
    Multiple-capture DFT system to reduce peak capture power during self-test or scan test 失效
    多捕捉DFT系统，可在自检或扫描测试期间降低峰值捕获能力

    公开(公告)号：US08091002B2

    公开(公告)日：2012-01-03

    申请号：US12797302

    申请日：2010-06-09

    申请人： Laung-Terng Wang ,  Shianling Wu ,  Zhigang Jiang ,  Jinsong Liu ,  Hao-Jan Chao ,  Lizhen Yu ,  Feifei Zhao ,  Fangfang Li ,  Jianping Yan

    发明人： Laung-Terng Wang ,  Shianling Wu ,  Zhigang Jiang ,  Jinsong Liu ,  Hao-Jan Chao ,  Lizhen Yu ,  Feifei Zhao ,  Fangfang Li ,  Jianping Yan

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3177 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594

    摘要： A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

    摘要翻译： 一种用于提供有序捕获时钟的方法，用于检测或定位N个时钟域内的故障，以及在扫描测试或自检模式下跨过集成电路或电路组件中的任何两个时钟域的故障，其中N> 1，每个时钟域具有一个 捕获时钟和多个扫描单元，每个捕获时钟包括多个捕获时钟脉冲; 所述方法包括：（a）在移入操作期间，在所述集成电路或电路组件中的所述N个时钟域内产生和移入N个测试刺激; （b）将所述捕获时钟的有序序列应用于所述N个时钟域内的所有所述扫描单元，所述捕获时钟的有序序列包括至少多个捕获时钟脉冲，所述捕获时钟脉冲以两个或更多个选定的捕获时钟以顺序排列，使得 在捕获操作期间，所有时钟域不会同时触发; 和（c）分析所有所述扫描单元的输出响应以定位其中的任何故障。

    METHOD AND APPARATUS FOR DELAY FAULT COVERAGE ENHANCEMENT
    9.
    发明申请
    METHOD AND APPARATUS FOR DELAY FAULT COVERAGE ENHANCEMENT 审中-公开
    延迟故障覆盖增强的方法和装置

    公开(公告)号：US20100138709A1

    公开(公告)日：2010-06-03

    申请号：US12554437

    申请日：2009-09-04

    申请人： Laung-Terng WANG ,  Michael S. Hsiao ,  Hao-Jan Chao ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

    发明人： Laung-Terng WANG ,  Michael S. Hsiao ,  Hao-Jan Chao ,  Zhigang Jiang ,  Shianling Wu ,  Jianping Yan

    IPC分类号： G01R31/3177 ,  G06F11/27

    CPC分类号： G01R31/318552

    摘要： A hybrid clocking scheme for simultaneously detecting a b-cycle path-delay fault in a b-cycle (false) path and a c-cycle path-delay fault in a c-cycle (false) path using at least n+1 at-speed clock pulses during a capture operation in a clock domain in a scan design or a scan-based BIST design, where 1

    摘要翻译： 一种用于同时检测b周期（假）路径中的b周期路径延迟故障和c周期（假）路径中的c周期路径延迟故障的混合时钟方案，其使用至少n + 1 at- 在扫描设计或基于扫描的BIST设计中的时钟域中的捕获操作期间，速度时钟脉冲，其中1 <= b <= c <= n。 扫描设计或BIST设计包括多个扫描链，每个扫描链包括串联耦合的多个扫描单元。 该设计包括一个或多个时钟域，每个时钟域以其预期的工作频率或速度运行。 混合时钟方案包括至少一个速率移位时钟脉冲或一个在速捕获时钟脉冲，紧接着在捕获操作期间至少两个速度捕捉时钟脉冲，以同时检测b周期路径延迟故障，以及 时钟域内的c循环路径延迟故障。

    Multiple-capture DFT system to reduce peak capture power during self-test or scan test
    10.
    发明授权
    Multiple-capture DFT system to reduce peak capture power during self-test or scan test 失效
    多捕捉DFT系统，可在自检或扫描测试期间降低峰值捕获能力

    公开(公告)号：US08458544B2

    公开(公告)日：2013-06-04

    申请号：US13309987

    申请日：2011-12-02

    申请人： Laung-Terng Wang ,  Hao-Jan Chao ,  Shianling Wu

    发明人： Laung-Terng Wang ,  Hao-Jan Chao ,  Shianling Wu

    IPC分类号： G01R31/28 ,  G06F17/50

    CPC分类号： G01R31/3177 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594

    摘要： A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, includes the steps of: (a) generating and shifting-in N test stimuli to all scan cells within the N clock domains during a shift-in operation; (b) applying an ordered sequence of capture clocks to all scan cells within the N clock domains, the ordered sequence of capture clocks including a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all scan cells to locate any faults therein.

    摘要翻译： 一种用于提供有序捕获时钟的方法，用于检测或定位N个时钟域内的故障，以及跨过扫描测试或自检模式中的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1，包括以下步骤： （a）在移入操作期间，在N个时钟域内产生和移动N个测试刺激到所有扫描单元; （b）将有序的捕获时钟序列应用于N个时钟域内的所有扫描单元，所述捕获时钟的有序序列包括来自两个或更多个选定的捕获时钟的多个捕获时钟脉冲，其以顺序排列，使得所有时钟域 在捕获操作期间不会同时触发; 和（c）分析所有扫描单元的输出响应以定位其中的任何故障。