公开(公告)号：US20240145425A1

公开(公告)日：2024-05-02

申请号：US18405875

申请日：2024-01-05

Applicant: Lodestar Licensing Group LLC

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

IPC: H01L23/00 ,  H01L25/18

CPC classification number: H01L24/49 ,  H01L24/06 ,  H01L25/18 ,  H01L2924/15165

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

公开(公告)号：US12266630B2

公开(公告)日：2025-04-01

申请号：US18405875

申请日：2024-01-05

Applicant: Lodestar Licensing Group LLC

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

IPC: H01L23/00 ,  H01L25/18

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

公开(公告)号：US20240057337A1

公开(公告)日：2024-02-15

申请号：US18492689

申请日：2023-10-23

Applicant: Lodestar Licensing Group LLC

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H10B43/27 ,  H01L29/06 ,  H01L21/762

CPC classification number: H10B43/27 ,  H01L29/0649 ,  H01L21/76224

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

公开(公告)号：US20240274538A1

公开(公告)日：2024-08-15

申请号：US18642617

申请日：2024-04-22

Applicant: Lodestar Licensing Group LLC

Inventor： Biow Hiem Ong ,  David A. Daycock ,  Chieh Hsien Quek ,  Chii Wean Calvin Chen ,  Christian George Emor ,  Wing Yu Lo

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H10B41/40 ,  H10B41/27 ,  H10B43/27

Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.