公开(公告)号：US20240057337A1

公开(公告)日：2024-02-15

申请号：US18492689

申请日：2023-10-23

Applicant: Lodestar Licensing Group LLC

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H10B43/27 ,  H01L29/06 ,  H01L21/762

CPC classification number: H10B43/27 ,  H01L29/0649 ,  H01L21/76224

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

公开(公告)号：US20240324223A1

公开(公告)日：2024-09-26

申请号：US18731940

申请日：2024-06-03

Applicant: Lodestar Licensing Group LLC

Inventor： S. M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC: H10B43/27 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  H01L21/768

CPC classification number: H10B43/27 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0466 ,  H01L21/76802 ,  H01L21/76877

Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230380167A1

公开(公告)日：2023-11-23

申请号：US18365698

申请日：2023-08-04

Applicant: Lodestar Licensing Group, LLC

Inventor： Albert Fayrushin ,  Haitao Liu ,  Mojtaba Asadirad

IPC: H10B43/27 ,  H01L29/10 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H10B43/30

CPC classification number: H10B43/27 ,  H01L29/1037 ,  H01L23/5226 ,  H01L23/528 ,  H01L21/02532 ,  H01L21/76877 ,  H01L21/02595 ,  H01L23/53271 ,  H10B43/30 ,  G11C16/0483

Abstract: A semiconductor device comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, and a channel structure within an opening vertically extending through the stack and comprising a first semiconductor material having a first band gap. The semiconductor device also comprises a conductive plug structure within the opening and in direct contact with the channel region, and a band offset structure within the opening and in direct physical contact with the channel structure and the conductive plug structure. The band offset structure comprises a second semiconductor material having a second band gap different than the first band gap. The semiconductor device further comprises a conductive line structure electrically coupled to the conductive plug structure. A method of forming a semiconductor device and an electronic system are also described.

公开(公告)号：US12004351B2

公开(公告)日：2024-06-04

申请号：US17869732

申请日：2022-07-20

Applicant: Lodestar Licensing Group LLC

Inventor： S. M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC: H10B43/27 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  H01L21/768

CPC classification number: H10B43/27 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0466 ,  H01L21/76802 ,  H01L21/76877

Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.