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公开(公告)号：US12131782B2
公开(公告)日：2024-10-29
申请号：US18195147
申请日：2023-05-09
发明人： Aaron Yip
IPC分类号： G11C16/04 , G11C16/14 , G11C16/26 , H10B41/27 , H10B41/35 , H10B43/35 , G11C16/08 , H10B43/27 , H10B43/50
CPC分类号： G11C16/0483 , G11C16/0458 , H10B41/27 , H10B41/35 , H10B43/35 , G11C16/08 , G11C16/14 , G11C16/26 , G11C2216/02 , H10B43/27 , H10B43/50
摘要： Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.
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公开(公告)号：US20240339390A1
公开(公告)日：2024-10-10
申请号：US18666369
申请日：2024-05-16
发明人： Owen R. Fay , Jack E. Murray
IPC分类号： H01L23/498 , H01L21/48 , H01L23/00 , H01L23/13 , H01L23/31 , H01L25/00 , H01L25/065 , H01L25/10 , H01L25/18
CPC分类号： H01L23/49827 , H01L21/4853 , H01L21/486 , H01L23/13 , H01L23/49838 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L25/50 , H01L23/3128 , H01L23/49811 , H01L24/13 , H01L24/16 , H01L24/48 , H01L25/0655 , H01L2224/131 , H01L2224/1413 , H01L2224/14179 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/45099 , H01L2224/48145 , H01L2224/48227 , H01L2225/06517 , H01L2225/0652 , H01L2225/06548 , H01L2225/06572 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/15153 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181
摘要： Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.
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公开(公告)号：US12105644B2
公开(公告)日：2024-10-01
申请号：US18198782
申请日：2023-05-17
CPC分类号： G06F12/1433 , G06F12/1466 , G06F21/79 , G11C11/4074 , G11C17/16 , G06F3/0622 , G06F3/0637 , G06F12/14 , G06F12/1458 , G06F2212/1052
摘要： Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.
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公开(公告)号：US20240324223A1
公开(公告)日：2024-09-26
申请号：US18731940
申请日：2024-06-03
发明人： S. M. Istiaque Hossain , Prakash Rau Mokhna Rau , Arun Kumar Dhayalan , Damir Fazil , Joel D. Peterson , Anilkumar Chandolu , Albert Fayrushin , George Matamis , Christopher Larsen , Rokibul Islam
IPC分类号： H10B43/27 , G11C5/02 , G11C5/06 , G11C16/04 , H01L21/768
CPC分类号： H10B43/27 , G11C5/025 , G11C5/06 , G11C16/0466 , H01L21/76802 , H01L21/76877
摘要： Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US12089403B2
公开(公告)日：2024-09-10
申请号：US17590266
申请日：2022-02-01
发明人： M. Jared Barclay , Merri L. Carlson , Saurabh Keshav , George Matamis , Young Joon Moon , Kunal R. Parekh , Paolo Tessariol , Vinayak Shamanna
IPC分类号： H10B41/27 , H01L21/311 , H10B41/10 , H10B43/10 , H10B43/27
CPC分类号： H10B41/27 , H01L21/31144 , H10B41/10 , H10B43/10 , H10B43/27
摘要： A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.
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公开(公告)号：US12089232B2
公开(公告)日：2024-09-10
申请号：US18306694
申请日：2023-04-25
发明人： Fa-Long Luo , Jaime Cummins , Tamara Schmitz , Jeremy Chritz
CPC分类号： H04W72/29 , H04W88/085 , Y02D30/70
摘要： Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system allocates the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.
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公开(公告)号：US12087386B2
公开(公告)日：2024-09-10
申请号：US18164051
申请日：2023-02-03
发明人： Gil Golov
摘要： A memory system having a processing device (e.g., CPU) and memory regions (e.g., in a DRAM device) on the same chip or die. The memory regions store data used by the processing device during machine learning processing (e.g., using a neural network). One or more controllers are coupled to the memory regions and configured to: read data from a first memory region (e.g., a first bank), including reading first data from the first memory region, where the first data is for use by the processing device in processing associated with machine learning; and write data to a second memory region (e.g., a second bank), including writing second data to the second memory region. The reading of the first data and writing of the second data are performed in parallel.
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公开(公告)号：US20240290722A1
公开(公告)日：2024-08-29
申请号：US18652551
申请日：2024-05-01
发明人： Jordan D. Greenlee , Lifang Xu , Rita J. Klein , Xiao Li , Everett A. McTeer
IPC分类号： H01L23/532 , H01L21/768 , H01L23/00 , H01L23/522 , H10B41/27 , H10B41/41
CPC分类号： H01L23/53266 , H01L21/76846 , H01L23/5226 , H01L23/562 , H10B41/27 , H10B41/41
摘要： An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.
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公开(公告)号：US20240290384A1
公开(公告)日：2024-08-29
申请号：US18658559
申请日：2024-05-08
CPC分类号： G11C13/0061 , G11C13/003 , H03L7/0816
摘要： Memory devices may have a memory array and a command delay circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the command delay circuitry. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.
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公开(公告)号：US12072380B2
公开(公告)日：2024-08-27
申请号：US17883175
申请日：2022-08-08
发明人： Antonino Mondello , Alberto Troia
CPC分类号： G01R31/3177 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F13/1668 , G11C29/14 , G11C29/16 , G11C29/32 , G11C2029/3202
摘要： The present disclosure relates to an apparatus comprising a host device and a memory component coupled to the host device. The memory component can comprise an array of memory cells, and an interface comprising a boundary scan architecture, wherein the boundary scan architecture includes an instruction register configured to store data indicative of a presence of a test data input (TDI) signal.
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