公开(公告)号：US11265010B2

公开(公告)日：2022-03-01

申请号：US16837417

申请日：2020-04-01

Applicant: MEDIATEK INC.

Inventor： Yun-Shiang Shu ,  Su-Hao Wu ,  Hung-Yi Hsieh ,  Albert Yen-Chih Chiou

IPC: H03M3/00

Abstract: An incremental analog-to-digital converter (ADC) with high accuracy. The incremental ADC has a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal, and a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal. A loop filter of the delta-sigma modulator has a preset circuit. In the preset circuit, the output terminal of the loop filter is preset rather than being reset during the reset phase of the incremental ADC.