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公开(公告)号：US11265010B2
公开(公告)日：2022-03-01
申请号：US16837417
申请日：2020-04-01
Applicant: MEDIATEK INC.
Inventor： Yun-Shiang Shu , Su-Hao Wu , Hung-Yi Hsieh , Albert Yen-Chih Chiou
IPC: H03M3/00
Abstract: An incremental analog-to-digital converter (ADC) with high accuracy. The incremental ADC has a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal, and a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal. A loop filter of the delta-sigma modulator has a preset circuit. In the preset circuit, the output terminal of the loop filter is preset rather than being reset during the reset phase of the incremental ADC.
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公开(公告)号：US10924129B2
公开(公告)日：2021-02-16
申请号：US16830243
申请日：2020-03-25
Applicant: MEDIATEK INC.
Inventor： Su-Hao Wu , Chan-Hsiang Weng
IPC: H03M1/12
Abstract: The present invention provides a time-interleaved analog-to-digital converter device, wherein the time-interleaved analog-to-digital converter device includes a random number generator, a plurality of ADCs and an output circuit. The random number generator is configured to generate a random number sequence. The plurality of ADCs are configured to receive an analog input signal to generate a plurality of digital signals, respectively, and each ADC is further configured to generate a selection signal according to the random number sequence. The output circuit is configured to select one of the digital signals according to the selection signals generated by the ADCs, to generate a digital output signal.
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Patent Agency Ranking
公开(公告)号：US10911059B2
公开(公告)日：2021-02-02
申请号：US16809581
申请日：2020-03-05
Applicant: MEDIATEK INC.
Inventor： Wei-Hsiang Huang , Yun-Shiang Shu , Su-Hao Wu
Abstract: A signal processing system includes an analog-to-digital converter (ADC) that is used to convert a first analog value into a first digital value and convert a second analog value into a second digital value. The ADC includes a first digital-to-analog converter (DAC) circuit and a second DAC circuit operating in different voltage domains. A first bit segment and a second bit segment of each digital value are determined via the first DAC circuit and the second DAC circuit, respectively. An analog injection value is injected to the second analog value, the analog injection value is converted from a digital injection value formed by a subset of bits of the second bit segment of the first digital value, and the second bit segment of the second digital value is derived from injecting the digital injection value to a digital value determined by the second DAC circuit.
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公开(公告)号：US20200295776A1
公开(公告)日：2020-09-17
申请号：US16809535
申请日：2020-03-04
Applicant: MEDIATEK INC.
Inventor： Tien-Yu Lo , Chan-Hsiang Weng , Su-Hao Wu
IPC: H03M3/00
Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.
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公开(公告)号：US10979069B2
公开(公告)日：2021-04-13
申请号：US16809535
申请日：2020-03-04
Applicant: MEDIATEK INC.
Inventor： Tien-Yu Lo , Chan-Hsiang Weng , Su-Hao Wu
Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.
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公开(公告)号：US20200343899A1
公开(公告)日：2020-10-29
申请号：US16830243
申请日：2020-03-25
Applicant: MEDIATEK INC.
Inventor： Su-Hao Wu , Chan-Hsiang Weng
IPC: H03M1/12
Abstract: The present invention provides a time-interleaved analog-to-digital converter device, wherein the time-interleaved analog-to-digital converter device includes a random number generator, a plurality of ADCs and an output circuit. The random number generator is configured to generate a random number sequence. The plurality of ADCs are configured to receive an analog input signal to generate a plurality of digital signals, respectively, and each ADC is further configured to generate a selection signal according to the random number sequence. The output circuit is configured to select one of the digital signals according to the selection signals generated by the ADCs, to generate a digital output signal.
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公开(公告)号：US20200295772A1
公开(公告)日：2020-09-17
申请号：US16809581
申请日：2020-03-05
Applicant: MEDIATEK INC.
Inventor： Wei-Hsiang Huang , Yun-Shiang Shu , Su-Hao Wu
Abstract: A signal processing system includes an analog-to-digital converter (ADC) that is used to convert a first analog value into a first digital value and convert a second analog value into a second digital value. The ADC includes a first digital-to-analog converter (DAC) circuit and a second DAC circuit operating in different voltage domains. A first bit segment and a second bit segment of each digital value are determined via the first DAC circuit and the second DAC circuit, respectively. An analog injection value is injected to the second analog value, the analog injection value is converted from a digital injection value formed by a subset of bits of the second bit segment of the first digital value, and the second bit segment of the second digital value is derived from injecting the digital injection value to a digital value determined by the second DAC circuit.
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