公开(公告)号：US10425615B2

公开(公告)日：2019-09-24

申请号：US15806718

申请日：2017-11-08

Applicant: MEDIATEK INC.

Inventor： Wei-Ting Wang ,  Han-Lin Li ,  Yu-Jen Chen ,  Yu-Ming Lin

IPC: H04N7/01 ,  G09G5/00

Abstract: An image processing apparatus including first circuitry, second circuitry, third circuitry, and fourth circuitry is provided. The first circuitry determines a frame miss rate according to a current frame rate and a target frame rate of an image signal. The second circuitry decreases the target frame rate to the current frame rate when the frame miss rate is greater than a first threshold. The third circuitry increases the target frame rate to an upper-limit frame rate which is determined according to the frame rendering time or memory bandwidth capability, when the frame miss rate is less than a second threshold which is smaller than the first threshold. The fourth circuitry applies the decreased or increased target frame rate for an image to be displayed.

公开(公告)号：US20170212575A1

公开(公告)日：2017-07-27

申请号：US15403153

申请日：2017-01-10

Applicant: MEDIATEK INC.

Inventor： Wei-Ting Wang ,  Han-Lin Li ,  Yingshiuan Pan ,  Yueh-Feng Lee ,  Shun-Yao Yang ,  Jih-Ming Hsu

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/206 ,  Y02D10/152

Abstract: A power budget allocation method includes: obtaining a system setting associated with a multi-core processor system, obtaining a target power budget, and checking, by a power management controller, at least one power management table according to the system setting and the target power budget to generate a power management output for the multi-core processor system. The system setting includes a core combination setting of the multi-core processor system, and further includes a frequency setting of each processor core selected by the core combination setting.

公开(公告)号：US20180232032A1

公开(公告)日：2018-08-16

申请号：US15432945

申请日：2017-02-15

Applicant: MEDIATEK INC.

Inventor： Wei-Ting Wang ,  Yingshiuan Pan ,  Han-Lin Li ,  Chih-Yuan Hsiao ,  Che-Chuan Hu

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3234

Abstract: A power management method for an electronic apparatus is provided. The electronic apparatus includes a plurality of heat sources. The power management method includes the following steps: detecting a temperature of the electronic apparatus; detecting a power of the electronic apparatus; identifying an operating scenario of the electronic apparatus; and referring to the detected temperature, the detected power and the operating scenario to determine whether to allocate a power budget between the heat sources.

公开(公告)号：US20170302782A1

公开(公告)日：2017-10-19

申请号：US15097429

申请日：2016-04-13

Applicant: MEDIATEK INC.

Inventor： Wei-Ting Wang ,  Han-Lin Li ,  Hong-Jie Huang

IPC: H04M1/725

CPC classification number: H04M1/72569 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296

Abstract: Methods and apparatus are provided for chip aware thermal policies. In one novel aspect, the thermal performance mapping information is generated. In one embodiment, the process obtains a set of process-dependent power data for each process corner of a semiconductor chip, profiles performance data, and selects an operating thermal policy based on the performance data. The thermal policy, based on the process-dependent power data is a mapping formula, or a combination of a mapping formula and a mapping table. In another novel aspect, chip aware thermal control is based on process-dependent power data of process corners. In one embodiment, the mapping information of process-dependent power data to a corresponding thermal policy is stored in a memory. A thermal policy is applied based on the stored mapping information and an obtained process corner information. The mapping information is applied every time the thermal policy is needed or at boot-up time.

公开(公告)号：US20190303757A1

公开(公告)日：2019-10-03

申请号：US16221295

申请日：2018-12-14

Applicant: MediaTek Inc.

Inventor： Wei-Ting Wang ,  Han-Lin Li ,  Chih Chung Cheng ,  Shao-Yu Wang

IPC: G06N3/08 ,  G06F9/50 ,  G06N3/063 ,  G06F9/38

Abstract: A deep learning accelerator (DLA) includes processing elements (PEs) grouped into PE groups to perform convolutional neural network (CNN) computations, by applying multi-dimensional weights on an input activation to produce an output activation. The DLA also includes a dispatcher which dispatches input data in the input activation and non-zero weights in the multi-dimensional weights to the processing elements according to a control mask. The DLA also includes a buffer memory which stores the control mask which specifies positions of zero weights in the multi-dimensional weights. The PE groups generate output data of respective output channels in the output activation, and share a same control mask specifying same positions of the zero weights.

公开(公告)号：US09900424B2

公开(公告)日：2018-02-20

申请号：US15097429

申请日：2016-04-13

Applicant: MEDIATEK INC.

Inventor： Wei-Ting Wang ,  Han-Lin Li ,  Hong-Jie Huang

IPC: G08B17/00 ,  H04M1/725

CPC classification number: H04M1/72569 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296

Abstract: Methods and apparatus are provided for chip aware thermal policies. The thermal performance mapping information is generated. The process obtains a set of process-dependent power data for each process corner of a semiconductor chip, profiles performance data, and selects an operating thermal policy based on the performance data. The thermal policy, based on the process-dependent power data is a mapping formula, or a combination of a mapping formula and a mapping table. The chip aware thermal control is based on process-dependent power data of process corners. The mapping information of process-dependent power data to a corresponding thermal policy is stored in a memory. A thermal policy is applied based on the stored mapping information and an obtained process corner information. The mapping information is applied every time the thermal policy is needed or at boot-up time.