公开(公告)号：US09787434B2

公开(公告)日：2017-10-10

申请号：US14567172

申请日：2014-12-11

Applicant: MediaTek Inc.

Inventor： Chi-Feng Lin ,  Yu-Bang Nian

IPC: H03M13/00 ,  H04L1/00 ,  H03M13/09

CPC classification number: H04L1/0061 ,  H03M13/091 ,  H04L1/0045

Abstract: A communication device and associated method is provided. The communication device includes: a controller; a packet buffer, configured to store a current packet segment and a previous packet segment of an incoming packet; and a plurality of cyclic redundancy check (CRC) circuits, wherein each CRC circuit is individually fed with a portion of the current packet segment and/or a portion of the previous packet segment in a respective cycle of the incoming packet, and an initial value, wherein the plurality of CRC circuits are arranged in parallel.

公开(公告)号：US08989318B2

公开(公告)日：2015-03-24

申请号：US13969624

申请日：2013-08-19

Applicant: Mediatek Inc.

Inventor： Kuan-Hua Chao ,  Tzu-Li Hung ,  Yu-Bang Nian

IPC: H03D1/00 ,  H04L27/06 ,  H04B1/16 ,  H03K5/19

CPC classification number: H04B1/16 ,  H03K5/19

Abstract: A detecting circuit includes: a first offset generating circuit, arranged to apply a first offset to an input signal pair and accordingly generate a first output signal pair; and a first sampling circuit, coupled to the first offset generating circuit, the first sampling circuit arranged to sample the first output signal pair to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair, and the first sampling circuit is controlled by a first signal that is irrelevant to the input signal pair.

Abstract translation: 一种检测电路包括：第一偏移生成电路，被布置为向输入信号对施加第一偏移并且因此产生第一输出信号对; 以及耦合到所述第一偏移生成电路的第一采样电路，所述第一采样电路经布置以对所述第一输出信号对进行采样以产生第一采样信号，其中所述第一采样信号用于识别所述输入信号对上的数据信号 并且第一采样电路由与输入信号对无关的第一信号控制。

公开(公告)号：US20150121120A1

公开(公告)日：2015-04-30

申请号：US14065436

申请日：2013-10-29

Applicant: MEDIATEK INC.

Inventor： Chi-Feng Lin ,  Kung-Yen Hsu ,  Yu-Bang Nian

IPC: G06F1/08

CPC classification number: H04L47/00 ,  G06F5/06 ,  G06F5/14 ,  H04L25/05 ,  H04L69/28

Abstract: A data transmission apparatus disposed within two network layers operative at different data rates is provided. The data transmission apparatus is coupled to a clock generator which provides a reference clock for a lower network layer and is coupled to a frequency synthesizer with an integer division factor that generates a divided clock for an upper network layer according to the reference clock and the integer division factor. The data transmission apparatus includes a first processing circuit and a second processing circuit. The first processing circuit corresponding to the upper network layer receives and transmits data by using the divided clock as its operation frequency. The second processing circuit corresponding to the lower network layer receives and transmits data from the first processing circuit by using the reference clock as an operation frequency for encoding data. The divided clock is generated from the frequency synthesizer with the integer division factor.

Abstract translation: 提供了设置在以不同数据速率操作的两个网络层内的数据传输设备。 数据传输装置耦合到时钟发生器，该时钟发生器为下层网络层提供参考时钟，并且以一个整数分频因子耦合到一个频率合成器，该系数根据参考时钟和整数产生上层网络层的分时钟 分裂因子 数据传输装置包括第一处理电路和第二处理电路。 对应于上层网络层的第一处理电路通过使用分频时钟作为其操作频率来接收和发送数据。 对应于较低网络层的第二处理电路通过使用参考时钟作为编码数据的操作频率从第一处理电路接收和发送数据。 分频时钟由具有整数除法因子的频率合成器产生。

公开(公告)号：US20130322577A1

公开(公告)日：2013-12-05

申请号：US13969624

申请日：2013-08-19

Applicant: MEDIATEK INC.

Inventor： Kuan-Hua Chao ,  Tzu-Li Hung ,  Yu-Bang Nian

IPC: H04B1/16

CPC classification number: H04B1/16 ,  H03K5/19

Abstract: A detecting circuit includes: a first offset generating circuit, arranged to apply a first offset to an input signal pair and accordingly generate a first output signal pair; and a first sampling circuit, coupled to the first offset generating circuit, the first sampling circuit arranged to sample the first output signal pair to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair, and the first sampling circuit is controlled by a first signal that is irrelevant to the input signal pair.

Abstract translation: 一种检测电路包括：第一偏移生成电路，被布置为向输入信号对施加第一偏移并且因此产生第一输出信号对; 以及耦合到所述第一偏移生成电路的第一采样电路，所述第一采样电路经布置以对所述第一输出信号对进行采样以产生第一采样信号，其中所述第一采样信号用于识别所述输入信号对上的数据信号 并且第一采样电路由与输入信号对无关的第一信号控制。

公开(公告)号：US09042505B2

公开(公告)日：2015-05-26

申请号：US14065436

申请日：2013-10-29

Applicant: MEDIATEK INC.

Inventor： Chi-Feng Lin ,  Kung-Yen Hsu ,  Yu-Bang Nian

IPC: H04L7/00 ,  G06F1/08

CPC classification number: H04L47/00 ,  G06F5/06 ,  G06F5/14 ,  H04L25/05 ,  H04L69/28

Abstract: A data transmission apparatus disposed within two network layers operative at different data rates is provided. The data transmission apparatus is coupled to a clock generator which provides a reference clock for a lower network layer and is coupled to a frequency synthesizer with an integer division factor that generates a divided clock for an upper network layer according to the reference clock and the integer division factor. The data transmission apparatus includes a first processing circuit and a second processing circuit. The first processing circuit corresponding to the upper network layer receives and transmits data by using the divided clock as its operation frequency. The second processing circuit corresponding to the lower network layer receives and transmits data from the first processing circuit by using the reference clock as an operation frequency for encoding data. The divided clock is generated from the frequency synthesizer with the integer division factor.

Abstract translation: 提供了设置在以不同数据速率操作的两个网络层内的数据传输设备。 数据传输装置耦合到时钟发生器，该时钟发生器为下层网络层提供参考时钟，并且以一个整数分频因子耦合到一个频率合成器，该系数根据参考时钟和整数产生上层网络层的分时钟 分裂因子 数据传输装置包括第一处理电路和第二处理电路。 对应于上层网络层的第一处理电路通过使用分频时钟作为其操作频率来接收和发送数据。 对应于较低网络层的第二处理电路通过使用参考时钟作为编码数据的操作频率从第一处理电路接收和发送数据。 分频时钟由具有整数除法因子的频率合成器产生。