公开(公告)号：US10691465B2

公开(公告)日：2020-06-23

申请号：US16191509

申请日：2018-11-15

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Po-Wen Huang ,  Le Xing ,  Bichao Wang ,  Cheng-Chieh Yeh ,  Jie Zhang ,  Chen-Nan Hsiao

IPC: G06F9/44 ,  G06F9/4401 ,  G06F21/64 ,  G06F3/06

Abstract: A method for synchronization of system management data includes steps of generating a request for system management data in response to execution of a system booting program, transmitting the request to a baseboard management controller so as to enable the baseboard management controller to transmit the system management data stored in a second storage unit to a processor; receiving the system management data from the baseboard management controller, and determining whether the system management data is complete; and when it is determined that the system management data is complete, storing at least one of the sequential packets of the system management data in a first storage unit, and proceeding with execution of the system booting program.

公开(公告)号：US11061689B2

公开(公告)日：2021-07-13

申请号：US16573864

申请日：2019-09-17

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Po-Wen Huang ,  Chen-Nan Hsiao ,  Xu Zhang ,  Wei-Lung Shen

IPC: G06F9/4401 ,  G06F9/445

Abstract: A synchronization method, which is capable of data synchronization in both directions between a storage medium and a storage unit, includes steps of: determining whether first parameter data of the storage medium is identical to default parameter data stored in the storage medium; determining whether a value of a flag stored in the storage unit is equal to a first logical value; and performing data synchronization between the storage unit and the storage medium based on at least one of the two determinations.

公开(公告)号：US10162646B2

公开(公告)日：2018-12-25

申请号：US15624956

申请日：2017-06-16

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Po-Wen Huang ,  Kei-Way Chang ,  Shih-Ta Chu ,  Jun-Jie Wu ,  Chen-Nan Hsiao

IPC: G06F15/177 ,  G06F9/44 ,  G06F9/445 ,  G06F9/4401 ,  G06F8/65 ,  G06F1/24 ,  G06F8/654

Abstract: A system includes a programmable non-volatile memory, a switch, a control chipset, and a basic input/output (BIOS) module. The switch has a first terminal coupled to the programmable non-volatile memory, and a second terminal coupled to the control chipset. The control chipset is configured to store a SKU parameter set in the programmable non-volatile memory according to a predetermined memory allocation. The BIOS module is coupled to the control chipset, and is configured to load and update the SKU parameter set according to the predetermined memory configuration during a booting operation of the motherboard.