公开(公告)号：US20130015887A1

公开(公告)日：2013-01-17

申请号：US13181587

申请日：2011-07-13

申请人： Marco Piselli ,  Simone Massaro ,  Michael Lenz ,  Marco Puerschel ,  Dusan Graovac

发明人： Marco Piselli ,  Simone Massaro ,  Michael Lenz ,  Marco Puerschel ,  Dusan Graovac

IPC分类号： H03K17/26

CPC分类号： H03K17/28 ,  H03K17/162 ,  H03K2217/0063 ,  H03K2217/0072

摘要： A drive circuit includes a first input terminal configured to receive a first input signal, a first output terminal configured to provide a first drive signal, a second output terminal configured to provide a second drive signal, and a mode selection terminal configured to have a mode selection element connected thereto. The drive circuit is configured to generate the first and second drive signals dependent on the first input signal such that there is a dead time between a time when one of the first and second drive signals assumes an off-level and a time when the other one of the first and second drive signals assumes an on-level, and evaluate at least one electrical parameter of the mode selection element and is configured to adjust a first signal range of the first drive signal and a second signal range of the second drive signal dependent on the evaluated parameter and to adjust the dead time dependent on the evaluated parameter.

摘要翻译： 驱动电路包括被配置为接收第一输入信号的第一输入端，被配置为提供第一驱动信号的第一输出端，​​被配置为提供第二驱动信号的第二输出端，以及被配置为具有模式 选择元件。 驱动电路被配置为产生取决于第一输入信号的第一和第二驱动信号，使得在第一和第二驱动信号之一呈现关闭电平的时间与当另一个驱动信号的时间之间存在死区时间 第一和第二驱动信号的第一和第二驱动信号呈现电平，并且评估模式选择元件的至少一个电参数，并且被配置为调整第一驱动信号的第一信号范围和第二驱动信号相关的第二信号范围 并根据评估参数调整死区时间。

公开(公告)号：US09337824B2

公开(公告)日：2016-05-10

申请号：US13181587

申请日：2011-07-13

申请人： Marco Piselli ,  Simone Massaro ,  Michael Lenz ,  Marco Puerschel ,  Dusan Graovac

发明人： Marco Piselli ,  Simone Massaro ,  Michael Lenz ,  Marco Puerschel ,  Dusan Graovac

IPC分类号： H03K17/28 ,  H03K17/16

CPC分类号： H03K17/28 ,  H03K17/162 ,  H03K2217/0063 ,  H03K2217/0072

摘要： A drive circuit includes a first input terminal configured to receive a first input signal, a first output terminal configured to provide a first drive signal, a second output terminal configured to provide a second drive signal, and a mode selection terminal configured to have a mode selection element connected thereto. The drive circuit is configured to generate the first and second drive signals dependent on the first input signal such that there is a dead time between a time when one of the first and second drive signals assumes an off-level and a time when the other one of the first and second drive signals assumes an on-level, and evaluate at least one electrical parameter of the mode selection element and is configured to adjust a first signal range of the first drive signal and a second signal range of the second drive signal dependent on the evaluated parameter and to adjust the dead time dependent on the evaluated parameter.

摘要翻译： 驱动电路包括被配置为接收第一输入信号的第一输入端，被配置为提供第一驱动信号的第一输出端，​​被配置为提供第二驱动信号的第二输出端，以及被配置为具有模式 选择元件。 驱动电路被配置为产生取决于第一输入信号的第一和第二驱动信号，使得在第一和第二驱动信号之一呈现关闭电平的时间与当另一个驱动信号的时间之间存在死区时间 第一和第二驱动信号的第一和第二驱动信号呈现电平，并且评估模式选择元件的至少一个电参数，并且被配置为调整第一驱动信号的第一信号范围和第二驱动信号相关的第二信号范围 并根据评估参数调整死区时间。

公开(公告)号：US08188723B2

公开(公告)日：2012-05-29

申请号：US12358057

申请日：2009-01-22

申请人： Marco Piselli ,  Cristian Garbossa ,  Andrea Vecchiato ,  Emanuele Bodano ,  Andrea Morra ,  Simone Massaro ,  Maurizio Inversi

发明人： Marco Piselli ,  Cristian Garbossa ,  Andrea Vecchiato ,  Emanuele Bodano ,  Andrea Morra ,  Simone Massaro ,  Maurizio Inversi

IPC分类号： G05F1/40

CPC分类号： H02M3/156 ,  H02M3/33507

摘要： Preferred embodiments of the present invention are a switching converter, an integrated circuit package, and method for controlling a switching converter. An embodiment of the invention is a switching converter comprising a first compensation network having a first node coupled to an error voltage and a second node coupled to electrical ground and a second compensation network having an input coupled to the error voltage. A frequency domain transfer function of the first compensation network comprises a first zero and a plurality of first poles, and a frequency domain transfer function of the second compensation network comprises a second zero and a second pole.

摘要翻译： 本发明的优选实施例是开关转换器，集成电路封装以及用于控制开关转换器的方法。 本发明的实施例是一种开关转换器，其包括具有耦合到误差电压的第一节点和耦合到电接地的第二节点的第一补偿网络和具有耦合到所述误差电压的输入的第二补偿网络。 第一补偿网络的频域传递函数包括第一零点和多个第一极点，并且第二补偿网络的频域传递函数包括第二零点和第二极点。

公开(公告)号：US20100181975A1

公开(公告)日：2010-07-22

申请号：US12358057

申请日：2009-01-22

申请人： Marco Piselli ,  Cristian Garbossa ,  Andrea Vecchiato ,  Emanuele Bodano ,  Andrea Morra ,  Simone Massaro ,  Maurizio Inversi

发明人： Marco Piselli ,  Cristian Garbossa ,  Andrea Vecchiato ,  Emanuele Bodano ,  Andrea Morra ,  Simone Massaro ,  Maurizio Inversi

IPC分类号： G05F1/00

CPC分类号： H02M3/156 ,  H02M3/33507

摘要： Preferred embodiments of the present invention are a switching converter, an integrated circuit package, and method for controlling a switching converter. An embodiment of the invention is a switching converter comprising a first compensation network having a first node coupled to an error voltage and a second node coupled to electrical ground and a second compensation network having an input coupled to the error voltage. A frequency domain transfer function of the first compensation network comprises a first zero and a plurality of first poles, and a frequency domain transfer function of the second compensation network comprises a second zero and a second pole.

摘要翻译： 本发明的优选实施例是开关转换器，集成电路封装以及用于控制开关转换器的方法。 本发明的实施例是一种开关转换器，其包括具有耦合到误差电压的第一节点和耦合到电接地的第二节点的第一补偿网络和具有耦合到所述误差电压的输入的第二补偿网络。 第一补偿网络的频域传递函数包括第一零点和多个第一极点，并且第二补偿网络的频域传递函数包括第二零点和第二极点。

公开(公告)号：US20100079122A1

公开(公告)日：2010-04-01

申请号：US12242304

申请日：2008-09-30

申请人： Emanuele Bodano ,  Andrea Morra ,  Andrea Vecchiato ,  Marco Piselli

发明人： Emanuele Bodano ,  Andrea Morra ,  Andrea Vecchiato ,  Marco Piselli

IPC分类号： G05F1/00

CPC分类号： H02M3/156

摘要： A system and method for adapting a width of a clocking pulse for clocking a DC-DC converter, wherein the width of the clocking pulse is selected based upon the duty cycle of the DC-DC converter. When the DC-DC converter operates below a predefined threshold duty cycle, a clocking pulse of a first width is selected to allow operation of the converter at a minimum predefined duty cycle with a clocking frequency that minimizes output voltage ripple. The first width corresponds to an on-time of a switching transistor of the DC-DC converter when the converter is operated at the minimum duty cycle. When the DC-DC converter operates above the predefined threshold duty cycle, a clocking pulse of a second width is selected to allow operation of the converter at high duty cycles while simultaneously avoiding missed inductor current pulses and generation of sub-harmonic voltage oscillations.

摘要翻译： 一种用于调整用于计时DC-DC转换器的时钟脉冲的宽度的系统和方法，其中基于DC-DC转换器的占空比来选择时钟脉冲的宽度。 当DC-DC转换器工作在低于预定义的阈值占空比时，选择第一宽度的时钟脉冲以允许以最小化输出电压纹波的时钟频率在最小预定占空比下操作转换器。 当转换器以最小占空比工作时，第一宽度对应于DC-DC转换器的开关晶体管的接通时间。 当DC-DC转换器工作在预定义的阈值占空比以上时，选择第二宽度的时钟脉冲，以允许转换器在高占空比下工作，同时避免漏电感电流脉冲和产生亚谐波电压振荡。

公开(公告)号：US09134743B2

公开(公告)日：2015-09-15

申请号：US13459817

申请日：2012-04-30

申请人： Glovanni Bisson ,  Marco Flaibani ,  Marco Piselli

发明人： Glovanni Bisson ,  Marco Flaibani ,  Marco Piselli

IPC分类号： G05F1/56 ,  G05F1/575

CPC分类号： G05F1/575

摘要： A low-dropout voltage regulator includes a power transistor configured to receive an input voltage and to provide a regulated output voltage at an output voltage node. The power transistor includes a control electrode configured to receive a driver signal. A reference circuit is configured to generate a reference voltage. A feedback network is coupled to the power transistor and is configured to provide a first feedback signal and a second feedback signal. The first feedback signal represents the output voltage and the second feedback signal represents an output voltage gradient. An error amplifier is configured to receive the reference voltage and the first feedback signal representing the output voltage. The error amplifier is configured to generate the driver signal dependent on the reference voltage and the first feedback signal. The error amplifier includes an output stage that is biased with a bias current responsive to the second feedback signal.

摘要翻译： 低压差稳压器包括被配置为接收输入电压并且在输出电压节点处提供稳定的输出电压的功率晶体管。 功率晶体管包括被配置为接收驱动器信号的控制电极。 参考电路被配置为产生参考电压。 反馈网络耦合到功率晶体管，并且被配置为提供第一反馈信号和第二反馈信号。 第一反馈信号表示输出电压，第二反馈信号表示输出电压梯度。 误差放大器被配置为接收参考电压和表示输出电压的第一反馈信号。 误差放大器被配置为根据参考电压和第一反馈信号产生驱动器信号。 误差放大器包括响应于第二反馈信号利用偏置电流偏置的输出级。

公开(公告)号：US08164319B2

公开(公告)日：2012-04-24

申请号：US12242304

申请日：2008-09-30

申请人： Emanuele Bodano ,  Andrea Morra ,  Andrea Vecchiato ,  Marco Piselli

发明人： Emanuele Bodano ,  Andrea Morra ,  Andrea Vecchiato ,  Marco Piselli

IPC分类号： G05F1/575 ,  G05F1/56

CPC分类号： H02M3/156

摘要： A system and method for adapting a width of a clocking pulse for clocking a DC-DC converter, wherein the width of the clocking pulse is selected based upon the duty cycle of the DC-DC converter. When the DC-DC converter operates below a predefined threshold duty cycle, a clocking pulse of a first width is selected to allow operation of the converter at a minimum predefined duty cycle with a clocking frequency that minimizes output voltage ripple. The first width corresponds to an on-time of a switching transistor of the DC-DC converter when the converter is operated at the minimum duty cycle. When the DC-DC converter operates above the predefined threshold duty cycle, a clocking pulse of a second width is selected to allow operation of the converter at high duty cycles while simultaneously avoiding missed inductor current pulses and generation of sub-harmonic voltage oscillations.

摘要翻译： 一种用于调整用于计时DC-DC转换器的时钟脉冲的宽度的系统和方法，其中基于DC-DC转换器的占空比来选择时钟脉冲的宽度。 当DC-DC转换器工作在低于预定义的阈值占空比时，选择第一宽度的时钟脉冲以允许以最小化输出电压纹波的时钟频率在最小预定占空比下操作转换器。 当转换器以最小占空比工作时，第一宽度对应于DC-DC转换器的开关晶体管的接通时间。 当DC-DC转换器工作在预定的阈值占空比以上时，选择第二宽度的时钟脉冲，以允许转换器在高占空比下运行，同时避免漏电感电流脉冲和产生亚谐波电压振荡。

公开(公告)号：US20130285631A1

公开(公告)日：2013-10-31

申请号：US13459817

申请日：2012-04-30

申请人： Giovanni Bisson ,  Marco Flaibani ,  Marco Piselli

发明人： Giovanni Bisson ,  Marco Flaibani ,  Marco Piselli

IPC分类号： G05F1/10

CPC分类号： G05F1/575

摘要： A low-dropout voltage regulator includes a power transistor configured to receive an input voltage and to provide a regulated output voltage at an output voltage node. The power transistor includes a control electrode configured to receive a driver signal. A reference circuit is configured to generate a reference voltage. A feedback network is coupled to the power transistor and is configured to provide a first feedback signal and a second feedback signal. The first feedback signal represents the output voltage and the second feedback signal represents an output voltage gradient. An error amplifier is configured to receive the reference voltage and the first feedback signal representing the output voltage. The error amplifier is configured to generate the driver signal dependent on the reference voltage and the first feedback signal. The error amplifier includes an output stage that is biased with a bias current responsive to the second feedback signal.