公开(公告)号：US20070043801A1

公开(公告)日：2007-02-22

申请号：US11479933

申请日：2006-06-30

Applicant: Tariq Kurd ,  Mark Homewood

Inventor： Tariq Kurd ,  Mark Homewood

IPC: G06F7/38

CPC classification number: G06F7/5334 ,  G06F7/49947 ,  G06F7/49957 ,  G06F7/49963

Abstract: An arithmetic unit comprising: an encoding circuit arranged to receive first and second operands each having a bit length of m bits and to generate therefrom a number n of partial products of varying bit length of m bits or less; an addition circuit having m columns each having n inputs, wherein bits of said partial products are applied to said inputs for combining said partial products into a result leaving certain of said inputs unused; and a rounding bit generator connected to supply a rounding bit to at least one of said unused inputs in one of said m columns at a bit position to cause said result to be rounded.

Abstract translation: 一种算术单元，包括：编码电路，被配置为接收第一和第二操作数，每个操作数具有m位的位长度，并由其产生m位或更少的位长度变化的n个部分乘积; 具有m列的加法电路，每一列具有n个输入，其中所述部分乘积的位被施加到所述输入，用于将所述部分乘积组合成使得某些所述输入未被使用的结果; 以及一个四舍五入比特发生器，其连接以在位位置向所述m列中的一个列中的至少一个所述未使用的输入提供舍入位，以使所述结果舍入。

公开(公告)号：US20060036881A1

公开(公告)日：2006-02-16

申请号：US11140620

申请日：2005-05-27

Applicant: Mark Homewood

Inventor： Mark Homewood

IPC: G06F1/26

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F1/3237 ,  G06F9/325 ,  Y02D10/128

Abstract: Disclosed in this patent document is a processor circuitry, and a method of operating such processor circuitry, comprising execution circuitry, at least one interrupt controller and an idle monitor, said monitor arranged to determine when said pipeline is idle by detecting an opcode and to determine if said execution circuitry is able to enter the idle state and if so to generate a signal to cause at least the execution circuitry to enter said idle state.

Abstract translation: 在该专利文献中公开了一种处理器电路和操作这种处理器电路的方法，包括执行电路，至少一个中断控制器和空闲监视器，所述监视器被布置成通过检测操作码来确定所述管线何时空闲，并且确定 如果所述执行电路能够进入空闲状态，并且如果是这样，则产生使至少执行电路进入所述空闲状态的信号。

公开(公告)号：US20060010304A1

公开(公告)日：2006-01-12

申请号：US10922242

申请日：2004-08-19

Applicant: Mark Homewood ,  Paolo Faraboschi

Inventor： Mark Homewood ,  Paolo Faraboschi

IPC: G06F12/00

CPC classification number: G06F9/30043 ,  G06F9/30032 ,  G06F9/30145 ,  G06F12/04

Abstract: A method of loading an unaligned word from a specified unaligned word address in a memory, said unaligned word comprising a plurality of indexed portions crossing a word boundary, the method comprising: loading a first aligned word commencing at an aligned word address rounded from said specified unaligned word address; identifying an index representing the location of the unaligned word address relative to the aligned word address; loading a second aligned word commencing at an aligned word address rounded from a second unaligned word address; and combining indexed portions of the first and second aligned words using the identified index to construct the unaligned word.

Abstract translation: 一种从存储器中指定的未对齐字地址加载未对齐字的方法，所述未对齐字包括与字边界交叉的多个索引部分，所述方法包括：加载从所述指定的四边形对齐的字地址开始的第一对齐字 未对齐的字地址; 识别表示未对齐字地址相对于对齐字地址的位置的索引; 加载从第二未对齐字地址四舍五入的对齐字地址开始的第二对齐字; 并且使用所识别的索引来组合第一和第二对齐字的索引部分以构造未对齐字。

公开(公告)号：US20080010443A1

公开(公告)日：2008-01-10

申请号：US11900978

申请日：2007-09-14

Applicant: Mark Homewood ,  Gary Vondran ,  Geoffrey Brown ,  Paolo Faraboschi

Inventor： Mark Homewood ,  Gary Vondran ,  Geoffrey Brown ,  Paolo Faraboschi

IPC: G06F9/00

CPC classification number: G06F9/30058 ,  G06F9/3885

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract translation: 公开了一种数据处理器，其具有包括至少一个分支簇，至少一个非分支簇和远程条件分支控制电路的集群架构。 每个集群都能够计算分支条件，尽管只有分支集群可用于执行分支地址计算。 响应于感测非分支集群中的条件分支指令，可以操作与每个集群相关联的远程条件分支控制电路，以（i）使分支集群计算分支地址和下一个程序计数器 （ii）使非分支集群计算分支条件，并且（iii）将所计算的分支条件从非分支集群传递到分支集群。 然后，数据处理器使用计算出的分支条件来选择分支地址或下一个程序计数器地址之一。

公开(公告)号：US20050182919A1

公开(公告)日：2005-08-18

申请号：US11020638

申请日：2004-12-22

Applicant: Andrew Dellow ,  Mark Homewood

Inventor： Andrew Dellow ,  Mark Homewood

IPC: G06F21/52 ,  G06F21/71 ,  G06F15/00

CPC classification number: G06F21/71 ,  G06F21/52

Abstract: A system and method for verifying the authenticity of instructions retrieved from a memory for execution by a processor. In one embodiment, an instruction monitor monitors execution parameters associated with the retrieved instruction and resets the system in response to an indication that an instruction is not authentic.

Abstract translation: 一种用于验证从存储器检索以由处理器执行的指令的真实性的系统和方法。 在一个实施例中，指令监视器监视与检索到的指令相关联的执行参数，并且响应于指令不可信的指示来重置系统。