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公开(公告)号：US20060181955A1
公开(公告)日：2006-08-17
申请号：US11349196
申请日：2006-02-08
申请人： Masao Shinozaki , Daisuke Shimadu
发明人： Masao Shinozaki , Daisuke Shimadu
IPC分类号： G11C8/00
摘要： A semiconductor integrated circuit device provided with a memory circuit having a word line selection circuit with reduced leakage current is provided. The memory circuit includes: second word lines with which memory cells are connected; multiple bit lines that are extended in a direction orthogonal thereto and electrically connected with memory cells corresponding to selected second word lines of a plurality of the second word lines; and word drivers, constructed of CMOS inverter circuits, that select or deselect the second word lines. The sources of p-channel MOSFETs that constitute a plurality of word drivers including second word lines corresponding to selected bit lines are supplied with a voltage at a level at which second word lines are selected. The sources of the p-channel MOSFETs of the other word drivers are supplied with a voltage corresponding to a level at which second word lines are deselected.
摘要翻译： 提供了具有具有减少的漏电流的字线选择电路的存储电路的半导体集成电路装置。 存储电路包括：与存储单元连接的第二字线; 多个位线在与其正交的方向上延伸并与对应于多个第二字线的所选择的第二字线的存储单元电连接; 和由CMOS反相器电路构成的字驱动器，其选择或取消选择第二字线。 构成多个字驱动器的p沟道MOSFET的源极包括对应于所选择的位线的第二字线，其电压被选择为第二字线的电平。 其他字驱动器的p沟道MOSFET的源极被提供有对应于第二字线被取消选择的电平的电压。
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公开(公告)号：US07423909B2
公开(公告)日：2008-09-09
申请号：US11349196
申请日：2006-02-08
申请人： Masao Shinozaki , Daisuke Shimadu
发明人： Masao Shinozaki , Daisuke Shimadu
IPC分类号： G11C11/34
摘要： A semiconductor integrated circuit device provided with a memory circuit having a word line selection circuit with reduced leakage current is provided. The memory circuit includes: second word lines with which memory cells are connected; multiple bit lines that are extended in a direction orthogonal thereto and electrically connected with memory cells corresponding to selected second word lines of a plurality of the second word lines; and word drivers, constructed of CMOS inverter circuits, that select or deselect the second word lines. The sources of p-channel MOSFETs that constitute a plurality of word drivers including second word lines corresponding to selected bit lines are supplied with a voltage at a level at which second word lines are selected. The sources of the p-channel MOSFETs of the other word drivers are supplied with a voltage corresponding to a level at which second word lines are deselected.
摘要翻译： 提供了具有具有减少的漏电流的字线选择电路的存储电路的半导体集成电路装置。 存储电路包括：与存储单元连接的第二字线; 多个位线在与其正交的方向上延伸并与对应于多个第二字线的所选择的第二字线的存储单元电连接; 和由CMOS反相器电路构成的字驱动器，其选择或取消选择第二字线。 构成多个字驱动器的p沟道MOSFET的源极包括对应于所选择的位线的第二字线，其电压被选择为第二字线的电平。 其他字驱动器的p沟道MOSFET的源极被提供有对应于第二字线被取消选择的电平的电压。
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公开(公告)号：US20080279033A1
公开(公告)日：2008-11-13
申请号：US12219050
申请日：2008-07-15
申请人： Masao Shinozaki , Daisuke Shimadu
发明人： Masao Shinozaki , Daisuke Shimadu
IPC分类号： G11C8/08
摘要： A semiconductor integrated circuit device provided with a memory circuit having a word line selection circuit with reduced leakage current is provided. The memory circuit includes: second word lines with which memory cells are connected; multiple bit lines that are extended in a direction orthogonal thereto and electrically connected with memory cells corresponding to selected second word lines of a plurality of the second word lines; and word drivers, constructed of CMOS inverter circuits, that select or deselect the second word lines. The sources of p-channel MOSFETs that constitute a plurality of word drivers including second word lines corresponding to selected bit lines are supplied with a voltage at a level at which second word lines are selected. The sources of the p-channel MOSFETs of the other word drivers are supplied with a voltage corresponding to a level at which second word lines are deselected.
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公开(公告)号：US20050047232A1
公开(公告)日：2005-03-03
申请号：US10452273
申请日：2003-06-03
IPC分类号： G11C11/41 , G11C5/14 , G11C7/10 , G11C11/413 , G11C11/417 , G11C29/02 , G11C29/04 , G11C7/00
CPC分类号： G11C29/022 , G11C5/14 , G11C7/1048 , G11C11/413 , G11C29/02
摘要： The invention provides a semiconductor integrated circuit device having a signal transmission path realizing high speed and low power consumption with a simple configuration. The device has a signal transmission path for transmitting a signal by discharging one of first signal lines corresponding to complementary input signals in a plurality of first signal lines precharged by a precharge circuit, and a self reset circuit for detecting the discharge level of the pair of signal lines corresponding to the complementary signals out of the plurality of first signal lines and operating the precharge circuit at a timing later than the period of discharging.
摘要翻译： 本发明提供一种半导体集成电路器件，其具有以简单的结构实现高速度和低功耗的信号传输路径。 该装置具有用于通过在由预充电电路预充电的多个第一信号线中对应于互补输入信号的第一信号线之一进行放电来发送信号的信号传输路径，以及用于检测一对 与多个第一信号线中的互补信号相对应的信号线，并且在比放电周期晚的定时操作预充电电路。
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5.发明授权Memory integrated circuit device having self reset circuit for precharging data buses based on the detection of their discharge levels 失效具有自复位电路的存储器集成电路装置，用于根据其放电电平的检测对数据总线进行预充电公开(公告)号：US06909653B2
公开(公告)日：2005-06-21
申请号：US10452273
申请日：2003-06-03
IPC分类号： G11C11/41 , G11C5/14 , G11C7/10 , G11C11/413 , G11C11/417 , G11C29/02 , G11C29/04 , G11C7/00
CPC分类号： G11C29/022 , G11C5/14 , G11C7/1048 , G11C11/413 , G11C29/02
摘要： The invention provides a semiconductor integrated circuit device having a signal transmission path realizing high speed and low power consumption with a simple configuration. The device has a signal transmission path for transmitting a signal by discharging one of first signal lines corresponding to complementary input signals in a plurality of first signal lines precharged by a precharge circuit, and a self reset circuit for detecting the discharge level of the pair of signal lines corresponding to the complementary signals out of the plurality of first signal lines and operating the precharge circuit at a timing later than the period of discharging.
摘要翻译： 本发明提供一种半导体集成电路器件，其具有以简单的结构实现高速度和低功耗的信号传输路径。 该装置具有用于通过在由预充电电路预充电的多个第一信号线中对应于互补输入信号的第一信号线之一进行放电来发送信号的信号传输路径，以及用于检测一对 与多个第一信号线中的互补信号相对应的信号线，并且在比放电周期晚的定时操作预充电电路。
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