公开(公告)号：US20240281171A1

公开(公告)日：2024-08-22

申请号：US18589184

申请日：2024-02-27

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G06F3/06 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/22 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.

公开(公告)号：US12056599B2

公开(公告)日：2024-08-06

申请号：US18061005

申请日：2022-12-02

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  William A. Melton

IPC: G06N3/00 ,  G06F3/06 ,  G06N3/04 ,  G06N3/063 ,  G11C7/06 ,  G11C8/08 ,  G11C11/54 ,  H03M1/46

CPC classification number: G06N3/063 ,  G06F3/0604 ,  G06F3/0661 ,  G06F3/0673 ,  G06N3/04 ,  G11C7/06 ,  G11C8/08 ,  G11C11/54 ,  H03M1/46

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a bit line and a word line of a number of word lines. A number of signals corresponding to bits of a second number may be driven on the number of word lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.

公开(公告)号：US12046323B2

公开(公告)日：2024-07-23

申请号：US17741099

申请日：2022-05-10

Applicant: SK hynix Inc.

Inventor： Jeong Jin Hwang ,  Sung Nyou Yu ,  Min Jun Choi

IPC: G11C8/10 ,  G11C8/08

CPC classification number: G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.

公开(公告)号：US12040041B2

公开(公告)日：2024-07-16

申请号：US17448754

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Kurt D. Beigel ,  Scott E. Sills

IPC: G11C5/02 ,  H01L21/308 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/786 ,  H03K19/0948 ,  H10B63/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C29/44

CPC classification number: G11C5/025 ,  H01L21/308 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/66742 ,  H01L29/78642 ,  H03K19/0948 ,  H10B63/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C29/4401

Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.

公开(公告)号：US20240203467A1

公开(公告)日：2024-06-20

申请号：US18587427

申请日：2024-02-26

Applicant: Micron Technolgy, Inc.

Inventor： Jiangang Wu ,  Lei Zhou ,  Jung Sheng Hoei ,  Kishore Kumar Muchherla ,  Qisong Lin

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/14 ,  G11C16/10

CPC classification number: G11C7/1096 ,  G11C8/08 ,  G11C8/14 ,  G11C16/10

Abstract: A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment, and the other indicia is a plane mask. Plane mask compatibility helps identify which pages can be programmed together in a multi-plane write operation.

公开(公告)号：US12014801B2

公开(公告)日：2024-06-18

申请号：US17814011

申请日：2022-07-21

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yang Zhao ,  Jaeyong Cha

IPC: G11C8/14 ,  G11C8/08

CPC classification number: G11C8/08 ,  G11C8/14

Abstract: Embodiments of the present application relate to the field of semiconductors, and provide a word line driver array and a memory. The word line driver array at least includes: a first transistor, a third transistor, a fourth transistor and a second transistor arranged sequentially, as well as a fourth word line, a first word line, a second word line and a third word line parallel to each other, wherein the fourth word line is connected to a drain of the fourth transistor, the first word line is connected to a drain of the first transistor, the second word line is connected to a drain of the second transistor, and the third word line is connected to a drain of the third transistor.

公开(公告)号：US12014796B2

公开(公告)日：2024-06-18

申请号：US17669628

申请日：2022-02-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Ku-Feng Lin

IPC: G11C7/06 ,  G11C7/10 ,  G11C8/08

CPC classification number: G11C7/1012 ,  G11C7/06 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/1096 ,  G11C8/08

Abstract: A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

公开(公告)号：US20240185914A1

公开(公告)日：2024-06-06

申请号：US18220387

申请日：2023-07-11

Applicant: SanDisk Technologies LLC

Inventor： Ming Wang ,  Liang Li

IPC: G11C11/56 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C11/5628 ,  G11C7/12 ,  G11C8/08

Abstract: A method for multi-state programming of a non-volatile memory structure, comprising: (1) initiating a programming operation with respect to multiple program states, (2) applying, to all selected word lines of the memory structure, a programming voltage bias (VPGM) level pre-determined to be suitable for programming a highest program state of the multiple program states, wherein the programming voltage bias level is applied according to a given program pulse width, and (3) with respect to each program state other than the highest program state of the multiple program states, applying a zero-volt bitline voltage bias (VBL) to one or more bitlines that are associated with one or more memory elements to be programmed to the program state, wherein the zero-volt bitline voltage bias is applied according to a respective program sub-pulse width that is less than the given program pulse width.

公开(公告)号：US20240153545A1

公开(公告)日：2024-05-09

申请号：US18415278

申请日：2024-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sanjeev Kumar Jain

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/20 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C7/222 ,  G11C7/1039 ,  G11C7/20 ,  G11C8/08 ,  G11C8/10 ,  G11C2207/2227

Abstract: Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal. The latch circuit may synchronize the local word line sleep signal with the delayed clock signal such that the local word line sleep signal is prevented from turning off power to the word line driver until memory read and write operations of the memory cell are disabled by the word line clock signal.

公开(公告)号：US11968820B2

公开(公告)日：2024-04-23

申请号：US17427934

申请日：2020-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Yuto Yakubo ,  Seiya Saito

IPC: G11C11/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H10B12/00 ,  G11C5/06 ,  G11C8/08

CPC classification number: H10B12/00 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  G11C5/06 ,  G11C8/08

Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.