公开(公告)号：US09373526B2

公开(公告)日：2016-06-21

申请号：US14556542

申请日：2014-12-01

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ming-Chieh Lin ,  Ta-Jen Yu

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11912 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads.

Abstract translation: 根据本发明的实施例，提供了一种用于形成芯片封装的方法。 该方法包括：提供导电板，其中多个导电焊盘设置在导电板的上表面上; 在导电板的下表面上形成多个导电凸块; 通过去除导电板的一部分来图案化导电板，其中图案化的导电板具有彼此电绝缘的多个导电部分，并且每个导电凸块电连接到图案化的导电部分的相应一个导电部分 导电板 形成绝缘支撑层以部分地包围所述导电凸块; 并将芯片设置在导电焊盘上。

公开(公告)号：US09437457B2

公开(公告)日：2016-09-06

申请号：US14015012

申请日：2013-08-30

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ming-Chieh Lin ,  Ta-Jen Yu

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11912 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装。 芯片封装包括：图案化导电板，其具有彼此电分离的多个导电部分; 设置在所述图案化导电板的上表面上的多个导电焊盘; 设置在导电垫上的芯片; 设置在所述图案化导电板的下表面上的多个导电凸块，其中每个所述导电凸块电连接到所述图案化导电板的相应一个导电部分; 以及部分地围绕导电凸块的绝缘支撑层。

公开(公告)号：US10074581B2

公开(公告)日：2018-09-11

申请号：US15225927

申请日：2016-08-02

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ming-Chieh Lin ,  Ta-Jen Yu

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of conducting pads disposed on an upper surface of the patterned conducting plate, wherein a recess extending from a surface of one of the conducting pads towards an inner portion of the corresponding one of the conducting pads, a chip disposed on the conducting pads, a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate, and an insulating support layer partially surrounding the conducting bumps.