公开(公告)号：US20240363676A1

公开(公告)日：2024-10-31

申请号：US18767205

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Cheng CHEN ,  Wei-Li HUANG ,  Chun-Yi WU ,  Kuang-Yi WU ,  Hon-Lin HUANG ,  Chih-Hung SU ,  Chin-Yu KU ,  Chen-Shien CHEN

IPC分类号： H01F41/04 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532

CPC分类号： H01L28/10 ,  H01F41/046 ,  H01L21/76823 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/53204 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The magnetic element has multiple sub-layers, and each sub-layer is wider than another sub-layer above it. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element, and the isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.

公开(公告)号：US20240363470A1

公开(公告)日：2024-10-31

申请号：US18765853

申请日：2024-07-08

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Yeong Beom Ko ,  Dong Jin Kim ,  Se Woong Cha

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L23/3185 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/18162

摘要： A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit.

公开(公告)号：US20240363464A1

公开(公告)日：2024-10-31

申请号：US18767895

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

摘要： A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.

公开(公告)号：US20240355697A1

公开(公告)日：2024-10-24

申请号：US18762478

申请日：2024-07-02

申请人： Intel Corporation

发明人： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC分类号： H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/3192 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L23/3128 ,  H01L2224/18 ,  H01L2224/214 ,  H01L2224/95001

摘要： A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US12125741B2

公开(公告)日：2024-10-22

申请号：US18362968

申请日：2023-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

IPC分类号： H01L23/053 ,  H01L21/02 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/31 ,  H01L23/532 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L21/76807 ,  H01L21/02645 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/5329 ,  H01L23/5384 ,  H01L24/32 ,  H01L2221/1015 ,  H01L2224/0231 ,  H01L2224/32225 ,  H01L2924/14

摘要： A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

公开(公告)号：US12119239B2

公开(公告)日：2024-10-15

申请号：US17532027

申请日：2021-11-22

申请人： Wolfspeed, Inc.

发明人： Soon Lee Liew ,  Eng Wah Woo ,  Alexander Komposch ,  Kok Meng Kam ,  Samantha Cheang

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L21/565 ,  H01L23/3114 ,  H01L23/49541

摘要： A package mold according to some embodiments includes a first mold body and a second mold body, a mold cavity in the first mold body, a gate in a first side of the mold cavity for supplying liquid mold compound into the mold cavity, a longitudinal vent for releasing gas from the mold cavity in a second side of the mold cavity opposite the first side of the mold cavity, and a transverse vent for releasing gas from the mold cavity in a third side of the mold cavity that extends between the first and second sides of the mold cavity. Methods of packaging an electronic device using the package mold and resulting packaged devices are also disclosed.

公开(公告)号：US20240332098A1

公开(公告)日：2024-10-03

申请号：US18128940

申请日：2023-03-30

申请人： Advanced Micro Devices, Inc. ,  ATI Technologies ULC

发明人： Suming HU ,  Roden TOPACIO ,  Manish DUBEY ,  Jianguo LI

IPC分类号： H01L23/051 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L23/051 ,  H01L21/563 ,  H01L23/3114

摘要： A chip package includes a package substrate, an integrated circuit (IC) die disposed on the package substrate, and a lid assembly disposed over the IC die. The lid assembly includes a top plate having a lower surface facing the IC die and an outer shoulder. The lid assembly also includes a retainer having a lower surface secured to the package substrate and an inner shoulder retaining to the outer shoulder. The inner shoulder is configured to limit upward movement of the top plate, and expansion of the retainer is decoupled from expansion of the top plate.

公开(公告)号：US12074143B2

公开(公告)日：2024-08-27

申请号：US17874598

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chi-Hui Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/40

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/4006

摘要： An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.

公开(公告)号：US12057362B2

公开(公告)日：2024-08-06

申请号：US17349211

申请日：2021-06-16

申请人： ROHM CO., LTD.

发明人： Osamu Miyata ,  Masaki Kasai ,  Shingo Higuchi

IPC分类号： H01L23/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/528 ,  H01L23/544

CPC分类号： H01L23/3178 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L23/544 ,  H01L23/562 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/05 ,  H01L2223/5446 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3025 ,  H01L24/13 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00 ,  H01L2224/0239 ,  H01L2924/01029 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014

摘要： A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.

公开(公告)号：US12051667B2

公开(公告)日：2024-07-30

申请号：US18373849

申请日：2023-09-27

申请人： Intel Corporation

发明人： Weng Hong Teh ,  Chia-Pin Chiu

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/50 ,  H01L25/16 ,  H01L25/18 ,  H01L21/56

CPC分类号： H01L24/25 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L21/568 ,  H01L23/3128 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

摘要： Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.