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公开(公告)号：US11025240B2
公开(公告)日：2021-06-01
申请号：US15671974
申请日：2017-08-08
申请人： MediaTek Inc.
摘要： Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths between a signal source, such as a driver, and a load. The paths may have different lengths, thus causing delay mismatches. An exemplary circuit of the type described herein may comprise delay elements and at least one feedback circuit designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load.
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公开(公告)号：US20240146269A1
公开(公告)日：2024-05-02
申请号：US18477538
申请日：2023-09-28
申请人： MediaTek Inc.
CPC分类号： H03F3/45932 , H03F1/26 , H03F3/45475 , H03F2203/45084
摘要： A differential all-pass coupling circuit with common mode feedback is disclosed. An example apparatus includes an anti-aliasing circuit configured to reduce a bandwidth of a first differential signal, and a switched-capacitor circuit coupled to the anti-aliasing circuit configured to control a first switch to charge a capacitor to a first voltage based on a first difference between (i) a common mode input voltage associated with a first common mode voltage of the first differential signal and (ii) a common mode reference voltage associated with a second common mode voltage of an input stage of the receiver, control a second switch to provide a second voltage to the capacitor based on a second difference between the first differential signal and the common mode input voltage, and output a second differential signal to the input stage based on the first differential signal adjusted by the second voltage.
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公开(公告)号：US20180167061A1
公开(公告)日：2018-06-14
申请号：US15671974
申请日：2017-08-08
申请人： MediaTek Inc.
CPC分类号： H03K5/159 , G06F1/10 , H03K3/0315 , H03K5/1502 , H03K5/151 , H03K2005/00019
摘要： Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths between a signal source, such as a driver, and a load. The paths may have different lengths, thus causing delay mismatches. An exemplary circuit of the type described herein may comprise delay elements and at least one feedback circuit designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load.
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4.发明公开公开(公告)号：US20240162906A1
公开(公告)日：2024-05-16
申请号：US18488785
申请日：2023-10-17
申请人： MediaTek Inc.
发明人： Ahmed Safwat Mohamed Aboelenein Elmallah , Mohammed Mohsen Abdulsalam Abdullatif , Tamer Mohammed Ali
IPC分类号： H03L7/093
CPC分类号： H03L7/093
摘要： The techniques described herein relate to systems, apparatus, articles of manufacture, and methods for optimum loop gain calibration for clock data recovery and phase locked loop. An example apparatus includes a phase detector with a phase detector output and configured to generate an error signal representative of a difference between an input signal and a feedback signal. The apparatus further includes a calibrator circuit with a calibrator input coupled to the phase detector output and configured to determine correlation value associated with the error signal, and determine a gain value based on an adjustment of an absolute value of the correlation value by a pseudorandom binary sequence signal.
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