公开(公告)号：US10043578B2

公开(公告)日：2018-08-07

申请号：US15345806

申请日：2016-11-08

Applicant: MEDIATEK INC.

Inventor： Shu-Lin Lai ,  Shu-Hsuan Lin ,  Shih-Huang Huang

IPC: G11C15/00 ,  G11C15/04 ,  G11C7/06

Abstract: A sense amplifier circuit includes a single-ended sense amplifier and an isolation switch. The isolation switch is coupled between a bias node and a first line of a memory device, receives an output of the single-ended sense amplifier and selectively isolates the bias node and the first line in response to the output of the single-ended sense amplifier. The first line is coupled to a plurality of memory cells of the memory device.

公开(公告)号：US09449679B2

公开(公告)日：2016-09-20

申请号：US14680289

申请日：2015-04-07

Applicant: MediaTek Inc.

Inventor： Shu-Hsuan Lin ,  Chia-Wei Wang

IPC: G11C7/00 ,  G11C11/418 ,  G11C7/12 ,  G11C11/417 ,  G11C29/02 ,  G11C11/41

CPC classification number: G11C11/418 ,  G11C7/12 ,  G11C11/41 ,  G11C11/417 ,  G11C29/021 ,  G11C29/028

Abstract: A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and second memory cells in the first area and second area, respectively. The plurality of first and second memory cells are coupled the first signal line, and each has a reference node. A first voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of first memory cells, wherein the first voltage adjustments circuit includes: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal; and a first bias element coupled to the reference nodes of the plurality of first memory cells. A second voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of second memory cells.

Abstract translation: 存储器件包括第一信号线; 存储单元阵列，分成第一区域和第二区域，并且分别在第一区域和第二区域中具有多个第一存储单元和第二存储单元。 多个第一和第二存储器单元耦合第一信号线，并且每个具有参考节点。 第一电压调节电路调节多个第一存储单元的参考节点处的电压，其中第一电压调整电路包括：耦合在多个第一存储单元的参考节点与地之间的第一开关，由地址 信号; 以及耦合到所述多个第一存储器单元中的参考节点的第一偏置元件。 第二电压调整电路调节多个第二存储单元的参考节点处的电压。

公开(公告)号：US09025394B2

公开(公告)日：2015-05-05

申请号：US13869171

申请日：2013-04-24

Applicant: MediaTek Inc.

Inventor： Shu-Hsuan Lin ,  Chia-Wei Wang

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/417 ,  G11C29/02 ,  G11C11/41

CPC classification number: G11C11/418 ,  G11C7/12 ,  G11C11/41 ,  G11C11/417 ,  G11C29/021 ,  G11C29/028

Abstract: A memory device is provided. The memory device includes a first signal line, a memory cell array, first and second voltage adjustment circuits. The memory cell array is divided into first and second areas and includes first memory cells in the first area and second memory cells in the second area. The first and second memory cells are coupled the first signal line. Each of the first and second memory cells has a reference node. The first voltage adjustment circuit adjusts voltages at the reference nodes of the first memory cells. The second voltage adjustment circuit adjusts voltages at the reference nodes of the second memory cells. The reference nodes of the first memory cells are coupled to a ground through the first voltage adjustment circuit. The reference nodes of the second memory cells are coupled to the ground through the second voltage adjustment circuit.

Abstract translation: 提供存储器件。 存储器件包括第一信号线，存储单元阵列，第一和第二电压调节电路。 存储单元阵列被划分为第一和第二区域，并且包括第一区域中的第一存储单元和第二区域中的第二存储单元。 第一和第二存储器单元耦合第一信号线。 第一和第二存储器单元中的每一个具有参考节点。 第一电压调节电路调节第一存储器单元的参考节点处的电压。 第二电压调节电路调节第二存储单元的参考节点处的电压。 第一存储单元的参考节点通过第一电压调节电路耦合到地。 第二存储单元的参考节点通过第二电压调节电路耦合到地。

公开(公告)号：US20140369103A1

公开(公告)日：2014-12-18

申请号：US13917662

申请日：2013-06-14

Applicant: Mediatek Inc.

Inventor： Shu-Hsuan Lin

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: An embodiment of the invention provides a binary CAM cell. The binary CAM cell includes a storage circuit, a first discharging circuit, and a second discharging circuit. The storage circuit is configured to provide a first stored bit and a second stored bit, which are complimentary bits of each other. The first discharging circuit is configured to either discharge or not discharge a match line according to the first stored bit provided by the storage circuit and a first searched bit provided by a first search line. The first discharging circuit includes a first PMOS transistor. The second discharging circuit is configured to either discharge or not discharge the match line according to the second stored bit provided by the storage circuit and a second searched bit provided by a second search line. The second discharging circuit includes a second PMOS transistor.

Abstract translation: 本发明的实施例提供二进制CAM单元。 二进制CAM单元包括存储电路，第一放电电路和第二放电电路。 存储电路被配置为提供彼此互补位的第一存储位和第二存储位。 第一放电电路被配置为根据存储电路提供的第一存储位和由第一搜索行提供的第一搜索位来放电或不放电匹配线。 第一放电电路包括第一PMOS晶体管。 第二放电电路被配置为根据由存储电路提供的第二存储位和由第二搜索线提供的第二搜索位来放电或不放电匹配线。 第二放电电路包括第二PMOS晶体管。