公开(公告)号：US10043578B2

公开(公告)日：2018-08-07

申请号：US15345806

申请日：2016-11-08

Applicant: MEDIATEK INC.

Inventor： Shu-Lin Lai ,  Shu-Hsuan Lin ,  Shih-Huang Huang

IPC: G11C15/00 ,  G11C15/04 ,  G11C7/06

Abstract: A sense amplifier circuit includes a single-ended sense amplifier and an isolation switch. The isolation switch is coupled between a bias node and a first line of a memory device, receives an output of the single-ended sense amplifier and selectively isolates the bias node and the first line in response to the output of the single-ended sense amplifier. The first line is coupled to a plurality of memory cells of the memory device.

公开(公告)号：US10181358B2

公开(公告)日：2019-01-15

申请号：US15492014

申请日：2017-04-20

Applicant: MEDIATEK Inc.

Inventor： Chia-Wei Wang ,  Shu-Lin Lai ,  Yi-Te Chiu

IPC: G11C17/00 ,  G11C17/18 ,  G11C7/06

Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.

公开(公告)号：US10770161B2

公开(公告)日：2020-09-08

申请号：US16211524

申请日：2018-12-06

Applicant: MEDIATEK Inc.

Inventor： Chia-Wei Wang ,  Shu-Lin Lai ,  Yi-Te Chiu

IPC: G11C17/00 ,  G11C17/18 ,  G11C7/06

Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.

公开(公告)号：US10176853B2

公开(公告)日：2019-01-08

申请号：US15499876

申请日：2017-04-27

Applicant: MEDIATEK INC.

Inventor： Chi-Hao Hong ,  Dao-Ping Wang ,  Yi-Wei Chen ,  Yi-Ping Kuo ,  Shu-Lin Lai

IPC: G11C7/12 ,  G11C7/06 ,  G11C7/10 ,  G11C7/08

Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.

公开(公告)号：US20240312557A1

公开(公告)日：2024-09-19

申请号：US18443347

申请日：2024-02-16

Applicant: MEDIATEK INC.

Inventor： Che-Wei Chou ,  Ya-Ting Yang ,  Shu-Lin Lai ,  Chi-Kai Hsieh ,  Yi-Ping Kuo ,  Chi-Hao Hong ,  Jia-Jing Chen ,  Yi-Te Chiu ,  Jiann-Tseng Huang

IPC: G11C29/00 ,  G11C29/56

CPC classification number: G11C29/702 ,  G11C29/56008 ,  G11C29/56016

Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.

公开(公告)号：US20190108890A1

公开(公告)日：2019-04-11

申请号：US16211524

申请日：2018-12-06

Applicant: MEDIATEK Inc.

Inventor： Chia-Wei Wang ,  Shu-Lin Lai ,  Yi-Te Chiu

IPC: G11C17/18 ,  G11C7/06

CPC classification number: G11C17/18 ,  G11C7/06 ,  G11C7/067

Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.

公开(公告)号：US20180114583A1

公开(公告)日：2018-04-26

申请号：US15492014

申请日：2017-04-20

Applicant: MEDIATEK Inc.

Inventor： Chia-Wei Wang ,  Shu-Lin Lai ,  Yi-Te Chiu

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G11C7/06 ,  G11C7/067

Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.

公开(公告)号：US20170345469A1

公开(公告)日：2017-11-30

申请号：US15499876

申请日：2017-04-27

Applicant: MEDIATEK INC.

Inventor： Chi-Hao Hong ,  Dao-Ping Wang ,  Yi-Wei Chen ,  Yi-Ping Kuo ,  Shu-Lin Lai

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/109

Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.