公开(公告)号：US11070224B1

公开(公告)日：2021-07-20

申请号：US16868894

申请日：2020-05-07

申请人： Mellanox Technologies, Ltd.

发明人： Hananel Faig ,  Adam Kaminer ,  David (Dima) Rochlin ,  Raanan Ivry

IPC分类号： H03M1/00 ,  H03M1/12 ,  H03M1/20 ,  H03M1/06

摘要： A method for providing back-compatibility for rational sampling rate disparities between two circuitries, comprises: a) providing a Phase Locked Loop (PLL) operating at a rate different than that of the Symbols generator, which is coupled to a Digital to Analog Converter (DAC) or an Analog to Digital Converter (ADC); b) providing an interpolation filter coupled to said converter, which filter is adapted to perform sampling rate conversion operations on the samples using zero-stuffing, filtering, and decimation, or the like computation-saving algorithm; and c) obtaining the sampling of the symbols at the required and compatible rate.