公开(公告)号：US20200251161A1

公开(公告)日：2020-08-06

申请号：US16268507

申请日：2019-02-06

Applicant: Mellanox Technologies, Ltd.

Inventor： George ELIAS ,  Hillel CHAPMAN ,  Eitan ZAHAVI ,  Elad MENTOVICH

IPC: G11C11/406

Abstract: One or more blocks of dynamic random access memory are embedded together with a processor and a data bus on an integrated circuit. The data bus has a bandwidth b for general operation including memory access, the block of dynamic random access memory further requiring data refresh at a refresh rate r. The block thus forms an eDRAM on the integrated circuit, typically an ASIC. A refresh controller embedded with the eDRAM may control refresh by clocking the data bus at a rate higher than the rate of the data bus to accommodate both the required memory access and the required data refresh.