公开(公告)号：US11892955B2

公开(公告)日：2024-02-06

申请号：US17741282

申请日：2022-05-10

Applicant: Microchip Technology Inc.

Inventor： Sanjay Goyal ,  Larrie Simon Carr ,  Patrick Bailey

IPC: G06F13/16 ,  G06F11/10 ,  G06F13/42

CPC classification number: G06F13/1621 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4221

Abstract: System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.