Daisy-chained synchronous ethernet clock recovery

    公开(公告)号:US11271712B2

    公开(公告)日:2022-03-08

    申请号:US16827624

    申请日:2020-03-23

    Abstract: A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

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