公开(公告)号：US20210303358A1

公开(公告)日：2021-09-30

申请号：US16833610

申请日：2020-03-29

Applicant: Micron Technology, Inc.

Inventor： Aliasger Zaidy ,  Andre Xian Ming Chang ,  Eugenio Culurciello

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/54 ,  G06F7/50 ,  G06F7/523 ,  G06N3/063

Abstract: An inference engine circuit architecture is disclosed which includes a matrix-matrix (MM) processor circuit and a MM accelerator circuit having multiple operating modes to provide a complete matrix multiplication. A representative MM accelerator circuit includes a first buffer circuit storing maps data; a first data network; multiple second buffer circuits each storing different kernel data; multiple second, serial data networks, with each coupled to a corresponding second buffer circuit; and a plurality of vector-vector (VV) acceleration circuits arranged in a plurality of arrays. Each VV acceleration circuit includes multiply and accumulate circuits; a shift register; a control multiplexer to provide a selected output, in response to a mode control word, of a bias parameter or a first accumulation sum; and a second adder circuit which adds the multiplicative product to the bias parameter or to the first accumulation sum to generate a second or next accumulation sum.

公开(公告)号：US11675624B2

公开(公告)日：2023-06-13

申请号：US16833610

申请日：2020-03-29

Applicant: Micron Technology, Inc.

Inventor： Aliasger Zaidy ,  Andre Xian Ming Chang ,  Eugenio Culurciello

IPC: G06F7/50 ,  G06F9/50 ,  G06F7/523 ,  G06F9/30 ,  G06F9/54 ,  G06N3/063

CPC classification number: G06F9/5027 ,  G06F7/50 ,  G06F7/523 ,  G06F9/30098 ,  G06F9/544 ,  G06N3/063

Abstract: An inference engine circuit architecture is disclosed which includes a matrix-matrix (MM) processor circuit and a MM accelerator circuit having multiple operating modes to provide a complete matrix multiplication. A representative MM accelerator circuit includes a first buffer circuit storing maps data; a first data network; multiple second buffer circuits each storing different kernel data; multiple second, serial data networks, with each coupled to a corresponding second buffer circuit; and a plurality of vector-vector (VV) acceleration circuits arranged in a plurality of arrays. Each VV acceleration circuit includes multiply and accumulate circuits; a shift register; a control multiplexer to provide a selected output, in response to a mode control word, of a bias parameter or a first accumulation sum; and a second adder circuit which adds the multiplicative product to the bias parameter or to the first accumulation sum to generate a second or next accumulation sum.

公开(公告)号：US11861337B2

公开(公告)日：2024-01-02

申请号：US17003476

申请日：2020-08-26

Applicant: Micron Technology, Inc.

Inventor： Andre Xian Ming Chang ,  Aliasger Zaidy ,  Eugenio Culurciello ,  Marko Vitez

IPC: G06F8/41 ,  G06F9/30 ,  G06F9/50 ,  G06N3/02

CPC classification number: G06F8/458 ,  G06F9/30087 ,  G06F9/5027 ,  G06N3/02

Abstract: A method of compiling neural network code to executable instructions for execution by a computational acceleration system having a memory circuit and one or more acceleration circuits having a maps data buffer and a kernel data buffer is disclosed, such as for execution by an inference engine circuit architecture which includes a matrix-matrix (MM) accelerator circuit having multiple operating modes to provide a complete matrix multiplication. A representative compiling method includes generating a list of neural network layer model objects; fusing available functions and layers in the list; selecting a cooperative mode, an independent mode, or a combined cooperative and independent mode for execution; selecting a data movement mode and an ordering of computations which reduces usage of the memory circuit; generating an ordered sequence of load objects, compute objects, and store objects; and converting the ordered sequence of load objects, compute objects, and store objects into the executable instructions.

公开(公告)号：US20250124102A1

公开(公告)日：2025-04-17

申请号：US18757909

申请日：2024-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dmitri Yudanov ,  Lawrence Celso Miranda ,  Sheyang Ning ,  Aliasger Zaidy

IPC: G06F17/16

Abstract: Memories might include a plurality of strings of series-connected memory cells, each corresponding to a respective digit of a plurality of digits of a multiplicand, and might further include a controller configured to cause the memory to generate respective current flows through the plurality of strings of series-connected memory cells for each digit of a plurality of digits of a multiplier having respective current levels indicative of values of each digit of the plurality of digits of the multiplier times the multiplicand, to convert the respective current levels to respective digital values indicative of the values and magnitudes of each digit of the plurality of digits of the multiplier times the multiplicand, and to sum the respective digital value of each digit of the plurality of digits of the multiplier.

公开(公告)号：US20220066760A1

公开(公告)日：2022-03-03

申请号：US17003476

申请日：2020-08-26

Applicant: Micron Technology, Inc.

Inventor： Andre Xian Ming Chang ,  Aliasger Zaidy ,  Eugenio Culurciello ,  Marko Vitez

IPC: G06F8/41 ,  G06F9/30 ,  G06F9/50 ,  G06N3/02

Abstract: A method of compiling neural network code to executable instructions for execution by a computational acceleration system having a memory circuit and one or more acceleration circuits having a maps data buffer and a kernel data buffer is disclosed, such as for execution by an inference engine circuit architecture which includes a matrix-matrix (MM) accelerator circuit having multiple operating modes to provide a complete matrix multiplication. A representative compiling method includes generating a list of neural network layer model objects; fusing available functions and layers in the list; selecting a cooperative mode, an independent mode, or a combined cooperative and independent mode for execution; selecting a data movement mode and an ordering of computations which reduces usage of the memory circuit; generating an ordered sequence of load objects, compute objects, and store objects; and converting the ordered sequence of load objects, compute objects, and store objects into the executable instructions.