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公开(公告)号：US20230026558A1
公开(公告)日：2023-01-26
申请号：US17960304
申请日：2022-10-05
发明人： Sheyang Ning , Lawrence Miranda
摘要： Control logic in a memory device causes a first set of pulses corresponding to a first voltage ramp slope level to be applied to a memory cell during a first time interval of an execution of a memory access operation. In response to determining a transition time has been reached, the control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first voltage ramp slope level and the second voltage ramp slope level are different.
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公开(公告)号：US20220351789A1
公开(公告)日：2022-11-03
申请号：US17306347
申请日：2021-05-03
摘要： Described are systems and methods for reducing maximum programming voltage in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying one or more memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and one or more target bitlines; causing drain-side select gates and source-side select gates of the memory array to be turned off; causing unselected wordlines of the memory array to discharge to a predefined voltage level; and causing one or more programming voltage pulses to be applied to the target wordline.
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公开(公告)号：US20220310167A1
公开(公告)日：2022-09-29
申请号：US17675447
申请日：2022-02-18
摘要： Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the memory array to be programmed to a first programming level. The control logic further performs a program verify operation corresponding to the first programming level and compares a threshold voltage of the memory cell to one or more program verify voltage levels of the program verify operation to determine whether a condition is satisfied. The control logic further executes a level shifting operation in response to the condition to be satisfied.
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公开(公告)号：US11462281B1
公开(公告)日：2022-10-04
申请号：US17307443
申请日：2021-05-04
发明人： Lawrence Celso Miranda , Eric N. Lee , Tong Liu , Sheyang Ning , Cobie B. Loper , Ugo Russo
摘要： Control logic in a memory device identifies a first group of wordlines associated with a first subset of memory cells of a set of memory cells to be programmed. A first dynamic start voltage operation including a first set of programming pulses and a first set of program verify operations is executed on a first portion of the first subset of memory cells to identify a first dynamic start voltage level, the executing of the first dynamic start voltage operation includes causing the first set of programming pulses to be applied to at least a portion of the first group of wordlines. A second set of programming pulses including at least one programming pulse having the first dynamic start voltage level are caused to be applied to the first group of wordlines to program a second portion of the first subset of memory cells of the set of memory cells. A second group of wordlines associated with a second subset of memory cells to be programmed is identified. A second dynamic start voltage operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second dynamic start voltage level.
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公开(公告)号：US20220187995A1
公开(公告)日：2022-06-16
申请号：US17119576
申请日：2020-12-11
发明人： Sheyang Ning , Lawrence Miranda
摘要： Control logic in a memory device identifies a request to execute a memory access operation on the memory cell. A first set of pulses corresponding to a first voltage ramp slope level is caused to be applied to the memory cell during a first time interval of the memory access operation. The control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first slope level and the second slope level are different.
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公开(公告)号：US11562791B1
公开(公告)日：2023-01-24
申请号：US17396825
申请日：2021-08-09
发明人： Hao T. Nguyen , Tomoko Ogura Iwasaki , Erwin E. Yu , Dheeraj Srinivasan , Sheyang Ning , Lawrence Celso Miranda , Aaron S. Yip , Yoshihiko Kamata
摘要： Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.
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公开(公告)号：US11494084B2
公开(公告)日：2022-11-08
申请号：US17119576
申请日：2020-12-11
发明人： Sheyang Ning , Lawrence Miranda
摘要： Control logic in a memory device identifies a request to execute a memory access operation on the memory cell. A first set of pulses corresponding to a first voltage ramp slope level is caused to be applied to the memory cell during a first time interval of the memory access operation. The control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first slope level and the second slope level are different.
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公开(公告)号：US20230039026A1
公开(公告)日：2023-02-09
申请号：US17396825
申请日：2021-08-09
发明人： Hao T. Nguyen , Tomoko Ogura Iwasaki , Erwin E. Yu , Dheeraj Srinivasan , Sheyang Ning , Lawrence Celso Miranda , Aaron S. Yip , Yoshihiko Kamata
摘要： Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.
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公开(公告)号：US20230034752A1
公开(公告)日：2023-02-02
申请号：US17833466
申请日：2022-06-06
摘要： A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, wordlines coupled with first and second pillars. Control logic is to cause: wordlines to be discharged after a program pulse is applied to selected wordline; a supply voltage be applied to second data line to cause a voltage of second pillar to float; a ground voltage be applied to first data line to inhibit soft erase via first pillar; unselected wordlines be charged to boost channel voltages in memory cells coupled with the second pillar; and one of the ground voltage or a negative voltage be applied to the selected wordline to increase soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be erased.
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公开(公告)号：US20230005553A1
公开(公告)日：2023-01-05
申请号：US17940338
申请日：2022-09-08
发明人： Lawrence Celso Miranda , Eric N. Lee , Tong Liu , Sheyang Ning , Cobie B. Loper , Ugo Russo
摘要： Control logic in a memory device executes a first operation comprising a first set of programming pulses and a first set of program verify operations on a first portion of a first subset of memory cells to be programmed to identify a first start voltage level. A second set of programming pulses including at least one programming pulse having the first start voltage level is caused to be applied to program a second portion of the first subset of memory cells. A second operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second start voltage level.
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