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公开(公告)号：US20240290389A1
公开(公告)日：2024-08-29
申请号：US18654697
申请日：2024-05-03
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Zhengyi Zhang , Tomoko Ogura Iwasaki
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3459
Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.
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公开(公告)号：US11961566B2
公开(公告)日：2024-04-16
申请号：US17833466
申请日：2022-06-06
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki
CPC classification number: G11C16/16 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3404 , G11C16/3481
Abstract: A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, wordlines coupled with first and second pillars. Control logic is to cause: wordlines to be discharged after a program pulse is applied to selected wordline; a supply voltage be applied to second data line to cause a voltage of second pillar to float; a ground voltage be applied to first data line to inhibit soft erase via first pillar; unselected wordlines be charged to boost channel voltages in memory cells coupled with the second pillar; and one of the ground voltage or a negative voltage be applied to the selected wordline to increase soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be erased.
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公开(公告)号：US20220351789A1
公开(公告)日：2022-11-03
申请号：US17306347
申请日：2021-05-03
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki
Abstract: Described are systems and methods for reducing maximum programming voltage in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying one or more memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and one or more target bitlines; causing drain-side select gates and source-side select gates of the memory array to be turned off; causing unselected wordlines of the memory array to discharge to a predefined voltage level; and causing one or more programming voltage pulses to be applied to the target wordline.
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公开(公告)号：US20220310167A1
公开(公告)日：2022-09-29
申请号：US17675447
申请日：2022-02-18
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda
Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the memory array to be programmed to a first programming level. The control logic further performs a program verify operation corresponding to the first programming level and compares a threshold voltage of the memory cell to one or more program verify voltage levels of the program verify operation to determine whether a condition is satisfied. The control logic further executes a level shifting operation in response to the condition to be satisfied.
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公开(公告)号：US20250124102A1
公开(公告)日：2025-04-17
申请号：US18757909
申请日：2024-06-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dmitri Yudanov , Lawrence Celso Miranda , Sheyang Ning , Aliasger Zaidy
IPC: G06F17/16
Abstract: Memories might include a plurality of strings of series-connected memory cells, each corresponding to a respective digit of a plurality of digits of a multiplicand, and might further include a controller configured to cause the memory to generate respective current flows through the plurality of strings of series-connected memory cells for each digit of a plurality of digits of a multiplier having respective current levels indicative of values of each digit of the plurality of digits of the multiplier times the multiplicand, to convert the respective current levels to respective digital values indicative of the values and magnitudes of each digit of the plurality of digits of the multiplier times the multiplicand, and to sum the respective digital value of each digit of the plurality of digits of the multiplier.
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Patent Agency Ranking
公开(公告)号：US20240220110A1
公开(公告)日：2024-07-04
申请号：US18540716
申请日：2023-12-14
Applicant: Micron Technology, Inc.
Inventor： Sheng-Huang Lee , Lu Tong , Lawrence Celso Miranda , Lakshmi Kalpana Vakati , Ekamdeep Singh , Ashish Ghai
CPC classification number: G06F3/061 , G06F3/0653 , G06F3/0679 , G06F11/073 , G06F11/0754
Abstract: Control logic in a memory device identifies a segment of the plurality of segments of a memory array of a memory device, and determines a health status for the segment from a plurality of possible health statuses, the plurality of possible health statuses comprising three or more health statuses. The control logic further provides the health status for the segment to a memory sub-system controller associated with the memory device, wherein the memory sub-system controller is to perform a corresponding action with respect to the segment based on the health status, and wherein the corresponding action is different for each of the plurality of possible health statuses.
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公开(公告)号：US11915758B2
公开(公告)日：2024-02-27
申请号：US18095049
申请日：2023-01-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Hao T. Nguyen , Tomoko Ogura Iwasaki , Erwin E. Yu , Dheeraj Srinivasan , Sheyang Ning , Lawrence Celso Miranda , Aaron S. Yip , Yoshihiko Kamata
CPC classification number: G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3459 , G11C11/5621 , G11C11/5671
Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.
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公开(公告)号：US20230274786A1
公开(公告)日：2023-08-31
申请号：US17681976
申请日：2022-02-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki , Ting Luo , Luyen Vu
CPC classification number: G11C29/42 , G11C29/4401 , G11C29/12005 , G11C7/1069 , G11C7/1096
Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.
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公开(公告)号：US11562791B1
公开(公告)日：2023-01-24
申请号：US17396825
申请日：2021-08-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Hao T. Nguyen , Tomoko Ogura Iwasaki , Erwin E. Yu , Dheeraj Srinivasan , Sheyang Ning , Lawrence Celso Miranda , Aaron S. Yip , Yoshihiko Kamata
Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.
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公开(公告)号：US20220351787A1
公开(公告)日：2022-11-03
申请号：US17745415
申请日：2022-05-16
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Lawrence Celso Miranda
Abstract: Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells.
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