公开(公告)号：US20190278655A1

公开(公告)日：2019-09-12

申请号：US15914402

申请日：2018-03-07

Applicant: Micron Technology, Inc.

Inventor： Larry J. KOUDELE ,  Mustafa N. KAYNAK ,  Michael SHEPEREK ,  Patrick R. KHAYAT ,  Sampath K. RATNAM

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation in response to determining that the first error rate exceeds the threshold.

公开(公告)号：US20230315570A1

公开(公告)日：2023-10-05

申请号：US18329886

申请日：2023-06-06

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. KAYNAK ,  Patrick R. KHAYAT ,  Sivagnanam PARTHASARATHY

IPC: G06F11/10

CPC classification number: G06F11/1076

Abstract: Methods, systems, and apparatus for error correction with syndrome computation in a memory device are described. A first syndrome for first encoded data is generated in a memory device. The first syndrome and the first encoded data are transmitted to a controller that is coupled with the memory device. A second syndrome for first and second encoded data is generated. The first encoded data and the second encoded data are interrelated according to an error correction code. The second syndrome is transmitted to the controller without the second encoded data and the controller is to decode the first encoded data based on at least one of the first syndrome, the second syndrome, or a combination thereof.

公开(公告)号：US20220350700A1

公开(公告)日：2022-11-03

申请号：US17246509

申请日：2021-04-30

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. KAYNAK ,  Patrick R. KHAYAT ,  Sivagnanam PARTHASARATHY

IPC: G06F11/10

Abstract: Methods, systems, and apparatus for error correction with syndrome computation in a memory device are described. A first syndrome for first encoded data is generated in a memory device. The first syndrome and the first encoded data are transmitted to a controller that is coupled with the memory device. A second syndrome for first and second encoded data is generated. The first encoded data and the second encoded data are interrelated according to an error correction code. The second syndrome is transmitted to the controller without the second encoded data and the controller is to decode the first encoded data based on at least one of the first syndrome, the second syndrome, or a combination thereof.