公开(公告)号：US20240331780A1

公开(公告)日：2024-10-03

申请号：US18738908

申请日：2024-06-10

Applicant: Micron Technology, Inc.

Inventor： Bruce A. LIIKANEN ,  Larry J. KOUDELE ,  Michael SHEPEREK

IPC: G11C16/34 ,  G11C5/04 ,  G11C11/56

CPC classification number: G11C16/3404 ,  G11C5/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3459 ,  G11C2211/5623 ,  G11C2211/5624 ,  G11C2211/5625

Abstract: A processing device determines a plurality of computing error metrics that are indicative of operational characteristics between programming distributions within the memory device. The processing device performs a program targeting operation on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions. Performing the program targeting operation comprises the processing device selecting a rule from a predefined set of rules based on the plurality of computing error metrics, wherein the predefined set of rules corresponds to an adjusting of a PV target of a last programming distribution. In addition, the processing device adjusts, based on the selected rule, the one or more PV targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.

公开(公告)号：US20200286551A1

公开(公告)日：2020-09-10

申请号：US16295829

申请日：2019-03-07

Applicant: Micron Technology, Inc.

Inventor： Michael SHEPEREK ,  Larry J. KOUDELE ,  Bruce A. LIIKANEN

IPC: G11C11/56 ,  G11C5/04

Abstract: A processing device determines that read level thresholds between first programming distributions of a second programming pass associated the memory component are calibrated. The processing device changes one or more of the read level thresholds between the first programming distributions. The processing device adjusts one or more read level threshold between second programming distributions of a first programming pass based on the change to the one or more read level thresholds between the first programming distributions.

公开(公告)号：US20200372962A1

公开(公告)日：2020-11-26

申请号：US16990859

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： Michael SHEPEREK ,  Larry J. KOUDELE ,  Bruce A. LIIKANEN

IPC: G11C16/34 ,  G11C5/04 ,  G11C11/56

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including determining first values of a metric that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory device. The operations further include determining second values of the metric based on the first values, and adjusting valley margins of the memory cell in accordance with the second values of the metric.

公开(公告)号：US20200286567A1

公开(公告)日：2020-09-10

申请号：US16295845

申请日：2019-03-07

Applicant: Micron Technology, Inc.

Inventor： Bruce A. LIIKANEN ,  Larry J. KOUDELE ,  Michael SHEPEREK

IPC: G11C16/34 ,  G11C11/56 ,  G11C5/04

Abstract: A processing device determines difference error counts that are indicative of relative widths of valleys. Each of the valleys is located between a respective pair of programming distributions of a memory cell of the memory component. A program targeting operation is performed on the memory cell to calibrate one or more program verify (PV) targets associated with the programming distributions. To perform the program targeting operation, a rule from a set of rules is selected based on the difference error counts. The set of rules corresponds to an adjusting of a PV target of a programming distribution adjacent to an initial programming distribution. One or more program verify (PV) targets associated with the programming distributions are adjusted based on the selected rule.

公开(公告)号：US20200286568A1

公开(公告)日：2020-09-10

申请号：US16295857

申请日：2019-03-07

Applicant: Micron Technology, Inc.

Inventor： Michael SHEPEREK ,  Larry J. KOUDELE ,  Bruce A. LIIKANEN

IPC: G11C16/34 ,  G11C5/04 ,  G11C11/56

Abstract: A processing device determines difference error counts for a difference error that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory component. A processing device scales each of the plurality of difference error counts by a respective scale factor of the scale factors. The processing device adjusts the valley margins of the memory cell in accordance with the scaled difference error counts.

公开(公告)号：US20190278655A1

公开(公告)日：2019-09-12

申请号：US15914402

申请日：2018-03-07

Applicant: Micron Technology, Inc.

Inventor： Larry J. KOUDELE ,  Mustafa N. KAYNAK ,  Michael SHEPEREK ,  Patrick R. KHAYAT ,  Sampath K. RATNAM

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation in response to determining that the first error rate exceeds the threshold.