公开(公告)号：US20240055190A1

公开(公告)日：2024-02-15

申请号：US17884450

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Huiqi Gong ,  Peng Zhao ,  Jingshan Wang ,  Giovanni Ferrari

IPC: H01G7/06

CPC classification number: H01G7/06

Abstract: Methods, systems, and devices for programmable chalcogenide capacitors are described. A first programming pulse may be applied, for a first duration, to a capacitor comprising a chalcogenide material to adjust a capacitance of the capacitor from a first capacitance to a second capacitance. A pulse may be applied to the capacitor based on applying the first programming pulse to the capacitor. A first voltage may be stored in the capacitor based on adjusting the capacitance of the capacitor from the first capacitance to the second capacitance, and the first voltage may be stored based on the capacitor having the second capacitance.

公开(公告)号：US20220319629A1

公开(公告)日：2022-10-06

申请号：US17221108

申请日：2021-04-02

Applicant: Micron Technology, Inc.

Inventor： Nicola Ciocchini ,  Peng Zhao

IPC: G11C29/50 ,  G11C13/00

Abstract: A memory device includes a memory array comprising a plurality of memory elements and a memory controller coupled to the memory array. The memory controller when in operation receives an indication of a defect in the memory array determines a first location of the defect when the defect is affecting only one memory element of the plurality of memory elements, determines a second location of the defect when the defect is affecting two or more memory elements of the plurality of memory elements, and performs a blown operation on a defective memory element at the second location when the defect is affecting two or more memory elements of the plurality of memory elements.

公开(公告)号：US11557369B2

公开(公告)日：2023-01-17

申请号：US17221108

申请日：2021-04-02

Applicant: Micron Technology, Inc.

Inventor： Nicola Ciocchini ,  Peng Zhao

IPC: G11C29/00 ,  G11C29/50 ,  G11C13/00

Abstract: A memory device includes a memory array comprising a plurality of memory elements and a memory controller coupled to the memory array. The memory controller when in operation receives an indication of a defect in the memory array determines a first location of the defect when the defect is affecting only one memory element of the plurality of memory elements, determines a second location of the defect when the defect is affecting two or more memory elements of the plurality of memory elements, and performs a blown operation on a defective memory element at the second location when the defect is affecting two or more memory elements of the plurality of memory elements.