公开(公告)号：US20240363188A1

公开(公告)日：2024-10-31

申请号：US18647731

申请日：2024-04-26

Applicant: Micron Technology, Inc.

Inventor： Steven Michael Kientz ,  Pitamber Shukla ,  Tarun Singh Yadav

IPC: G11C29/50

CPC classification number: G11C29/50004

Abstract: Memory cells may store multiple bits per cell. For example, three-level cell (TLC) memory stores three bits per cell using eight voltage levels. The number of memory cells at each voltage is approximately the total number of cells divided by the number of voltage levels. The number of memory cells above a certain read voltage is the CFByte value for the read voltage. Based on a difference between the CFByte value and a target CFByte value for the read voltage, an adjustment value is determined. Characteristics of an individual memory device may be determined by finding several CFByte values for a small range of read voltages. Using the gathered CFByte values, a DAC adjustment value is determined for the individual memory device.

公开(公告)号：US20240249789A1

公开(公告)日：2024-07-25

申请号：US18417517

申请日：2024-01-19

Applicant: Micron Technology, Inc.

Inventor： Tarun Singh Yadav ,  Scott Anthony Stoller ,  Pitamber Shukla ,  Fulvio Rori ,  Attila A. Herrera ,  Justin Bates

IPC: G11C29/12

CPC classification number: G11C29/1201 ,  G11C2029/1202

Abstract: Aspects of the present disclosure configure a memory sub-system controller to adaptively allocate word lines (WLs). The controller accesses reliability data of a set of main WLs of a block of the set of memory components. The controller determines that one or more WLs of the set of main WLs of the block are associated with respective reliability data that transgress a threshold and, in response to determining that the one or more WLs are associated with the respective reliability data that transgress the threshold, replaces the one or more WLs of the set of main WLs of the block with one or more dummy WLs. The controller programs data into the block using the one or more dummy WLs instead of the one or more WLs of the set of main WLs of the block.