公开(公告)号：US11847335B2

公开(公告)日：2023-12-19

申请号：US17212437

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Scott Anthony Stoller ,  Niccolo' Righetti ,  Giuseppina Puzzilli

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0679

Abstract: A trigger condition associated with latent read disturb in a memory device is detected. In response to detecting the trigger condition associated with latent read disturb, one or more blocks in the memory device that are impacted by the trigger condition are placed in a stable state to mitigate latent read disturb in the one or more blocks.

公开(公告)号：US20230113480A1

公开(公告)日：2023-04-13

申请号：US18080309

申请日：2022-12-13

Applicant: Micron Technology, Inc.

Inventor： Scott Anthony Stoller ,  Pitamber Shukla ,  Anita Marguerite Ekren

IPC: G06F11/07 ,  G06F11/30

Abstract: A log of error events associated with a memory device is maintained. Each error event included in the log is associated with one of multiple physical locations within the memory device. A physical location within the memory device is identified for background scanning based on the log of error events. A background scan is performed on the physical location identified based on the log of error events.

公开(公告)号：US20210089229A1

公开(公告)日：2021-03-25

申请号：US16579256

申请日：2019-09-23

Applicant: Micron Technology, Inc.

Inventor： Douglas Eugene Majerus ,  Scott Anthony Stoller ,  Brent Carl Byron

IPC: G06F3/06

Abstract: In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device detects a triggering condition for updating one or more media settings of a memory component of the plurality of memory components, and responsively instructs the memory component to load, from data storage on the memory component, a set of one or more media-setting values that correspond to the one or more media settings of the memory component.

公开(公告)号：US20190324876A1

公开(公告)日：2019-10-24

申请号：US16504067

申请日：2019-07-05

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Giuseppe Cariello ,  Deping He ,  Scott Anthony Stoller ,  Devin Batutis ,  Preston Allen Thomson

IPC: G06F11/20 ,  G11C29/00 ,  G11C16/34 ,  G06F11/10

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.

公开(公告)号：US10387281B2

公开(公告)日：2019-08-20

申请号：US15690903

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Giuseppe Cariello ,  Deping He ,  Scott Anthony Stoller ,  Devin Batutis ,  Preston Thomson

IPC: G06F11/20

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.

公开(公告)号：US10325670B2

公开(公告)日：2019-06-18

申请号：US16129422

申请日：2018-09-12

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Scott Anthony Stoller ,  Preston Thomson ,  Devin Batutis ,  Harish Reddy Singidi ,  Kulachet Tanpairoj

IPC: G11C29/00 ,  G11C29/38 ,  G06F11/07 ,  G11C29/44

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.

公开(公告)号：US20250021234A1

公开(公告)日：2025-01-16

申请号：US18768815

申请日：2024-07-10

Applicant: Micron Technology, Inc.

Inventor： Scott Anthony Stoller ,  Brent C. Byron ,  Sampath K. Ratnam ,  David Scott Ebsen

IPC: G06F3/06

Abstract: In-flight host data is programmed to one or more single-level cell (SLC) caches of a memory device using the single phase program operation during an asynchronous power loss (APL) event responsive to one or more parameters of a single-phase program operation being updated.

公开(公告)号：US20240249789A1

公开(公告)日：2024-07-25

申请号：US18417517

申请日：2024-01-19

Applicant: Micron Technology, Inc.

Inventor： Tarun Singh Yadav ,  Scott Anthony Stoller ,  Pitamber Shukla ,  Fulvio Rori ,  Attila A. Herrera ,  Justin Bates

IPC: G11C29/12

CPC classification number: G11C29/1201 ,  G11C2029/1202

Abstract: Aspects of the present disclosure configure a memory sub-system controller to adaptively allocate word lines (WLs). The controller accesses reliability data of a set of main WLs of a block of the set of memory components. The controller determines that one or more WLs of the set of main WLs of the block are associated with respective reliability data that transgress a threshold and, in response to determining that the one or more WLs are associated with the respective reliability data that transgress the threshold, replaces the one or more WLs of the set of main WLs of the block with one or more dummy WLs. The controller programs data into the block using the one or more dummy WLs instead of the one or more WLs of the set of main WLs of the block.

公开(公告)号：US11797376B2

公开(公告)日：2023-10-24

申请号：US18080309

申请日：2022-12-13

Applicant: Micron Technology, Inc.

Inventor： Scott Anthony Stoller ,  Pitamber Shukla ,  Anita Marguerite Ekren

IPC: G06F11/07 ,  G06F11/30

CPC classification number: G06F11/0793 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/0787 ,  G06F11/3037

Abstract: A log of error events associated with a memory device is maintained. Each error event included in the log is associated with one of multiple physical locations within the memory device. A physical location within the memory device is identified for background scanning based on the log of error events. A background scan is performed on the physical location identified based on the log of error events.

公开(公告)号：US11693587B2

公开(公告)日：2023-07-04

申请号：US17404875

申请日：2021-08-17

Applicant: Micron Technology, Inc.

Inventor： Sandeep Reddy Kadasani ,  Scott Anthony Stoller ,  Pitamber Shukla ,  Niccolo' Righetti ,  Chi Ming Chu

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A read operation is performed on a memory device in accordance with a pass-through voltage setting that defines a pass-through voltage applied to one or more cells of the memory device during read operations. A number of zero bits read from the memory device based on the read operation are counted and compared with a threshold value. Based on the number of zero bits exceeding the threshold value, the pass-through voltage is increased by adjusting the pass-through voltage setting.