公开(公告)号：US20240363185A1

公开(公告)日：2024-10-31

申请号：US18656177

申请日：2024-05-06

申请人： Micron Technology, Inc.

发明人： Deping He ,  Jonathan S. Parry ,  Chun Sum Yeung

IPC分类号： G11C29/42 ,  G06F11/07 ,  G11C29/12 ,  G11C29/20 ,  G11C29/44

CPC分类号： G11C29/42 ,  G06F11/076 ,  G11C29/1201 ,  G11C29/20 ,  G11C29/4401

摘要： Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

公开(公告)号：US20240347123A1

公开(公告)日：2024-10-17

申请号：US18647867

申请日：2024-06-07

申请人： Micron Technology, Inc.

发明人： Taeksang Song ,  Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Kang-Yong Kim

IPC分类号： G11C29/42 ,  G11C29/12 ,  G11C29/44

CPC分类号： G11C29/42 ,  G11C29/1201 ,  G11C29/4401

摘要： Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.

公开(公告)号：US12073901B2

公开(公告)日：2024-08-27

申请号：US17658846

申请日：2022-04-12

申请人： QUALCOMM Incorporated

发明人： Jungwon Suh

IPC分类号： G11C29/42 ,  G11C7/10 ,  G11C8/18 ,  G11C29/12

CPC分类号： G11C29/42 ,  G11C7/1048 ,  G11C7/1063 ,  G11C8/18 ,  G11C29/1201

摘要： A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.

公开(公告)号：US20240274212A1

公开(公告)日：2024-08-15

申请号：US18241621

申请日：2023-09-01

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yumin KIM ,  Jungyu LEE ,  Jihyun PARK ,  Chiweon YOON ,  Eunchan LEE

IPC分类号： G11C29/12 ,  G11C7/04 ,  G11C29/02

CPC分类号： G11C29/12005 ,  G11C7/04 ,  G11C29/028 ,  G11C29/1201

摘要： A voltage generation circuit includes a current generation circuit, a slope trimming circuit and an offset trimming circuit. The current generation circuit is connected between an input voltage node and an output node that outputs a complementary to absolute temperature (CTAT) output voltage that decreases as an operation temperature increases. The current generation circuit generates a reference current flowing through the output node, the reference current having a constant magnitude regardless of the operation temperature. The slope trimming circuit is connected between the output node and an intermediate node. The slope trimming circuit adjusts a slope of the CTAT output voltage based on a first trimming code. The offset trimming circuit is connected between the intermediate node and a ground voltage node. The offset trimming circuit configured to adjust an offset voltage of the CTAT output voltage based on a second trimming code.

公开(公告)号：US20240265991A1

公开(公告)日：2024-08-08

申请号：US18640651

申请日：2024-04-19

申请人： Micron Technology, Inc.

发明人： Scott E. Schaefer

IPC分类号： G11C29/44 ,  G11C29/12 ,  G11C29/18 ,  G11C29/42

CPC分类号： G11C29/4401 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/42 ,  G11C2029/1806

摘要： Methods, systems, and devices for bit retiring to mitigate bit errors are described. A memory device may retrieve a set of bits from a first row of an address space and may determine that the set of bits includes one or more errors. The memory device may remap at least a portion of the first row from a first row index to a second row index, where the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device. Additionally or alternatively, the memory device may receive a first command to access a first logical address of a memory array that is associated with a first row index. The memory device may determine that the first row includes one or more errors and may transmit a signal indicating that the first row includes the one or more errors.

公开(公告)号：US20240257890A1

公开(公告)日：2024-08-01

申请号：US18620765

申请日：2024-03-28

申请人： INTEL CORPORATION

发明人： Zhiguo Wei ,  Yanyang Tan ,  John Vancleve Lovelace

IPC分类号： G11C29/12 ,  G11C29/30 ,  G11C29/44

CPC分类号： G11C29/1201 ,  G11C29/30 ,  G11C29/44

摘要： Systems, apparatus, articles of manufacture, and methods are disclosed to select addresses for memory training. An example non-transitory computer readable medium comprising instructions that, when executed, cause a machine to determine a first memory address at which to perform memory input/output training based on an identification of a second memory address that is associated with an error, and cause the memory input/output training to be performed at the first memory address.

公开(公告)号：US20240249791A1

公开(公告)日：2024-07-25

申请号：US18624070

申请日：2024-04-01

申请人： SambaNova Systems, Inc.

发明人： Thomas ZIAJA ,  Uma DURAIRAJAN ,  Dinesh R. AMIRTHARAJ

IPC分类号： G11C29/32 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/27 ,  G11C7/10 ,  G11C7/22 ,  G11C11/408 ,  G11C29/12 ,  G11C29/36 ,  G11C29/42

CPC分类号： G11C29/32 ,  G11C7/1039 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/36 ,  G11C29/42 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318566 ,  G01R31/3187 ,  G06F11/27 ,  G11C7/1051 ,  G11C7/22 ,  G11C11/4082 ,  G11C2029/3202

摘要： An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.

公开(公告)号：US20240194283A1

公开(公告)日：2024-06-13

申请号：US18219456

申请日：2023-07-07

申请人： Western Digital Technologies, Inc.

发明人： Chin-Yi Chen ,  Ravi Kumar ,  Deepanshu Dutta

IPC分类号： G11C29/12

CPC分类号： G11C29/1201 ,  G11C2029/1202

摘要： A memory apparatus and operating method are provided. The apparatus includes memory cells connected to one of a plurality of word lines and disposed in memory holes coupled to bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the bit lines and for a group of the memory cells divided into a plurality of subsets, is configured to determine whether comparatively fewer read errors of the memory cells arise while pre-charging ones of the bit lines associated with each of the plurality of subsets. The control means is also configured to pre-charge ones of the bit lines associated with one the plurality of subsets with comparatively fewer read errors and read the memory cells associated therewith during a scan operation.

公开(公告)号：US20240177790A1

公开(公告)日：2024-05-30

申请号：US18058740

申请日：2022-11-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Wei-Chun CHEN

IPC分类号： G11C29/12 ,  G11C29/46

CPC分类号： G11C29/1201 ,  G11C29/12015 ,  G11C29/46

摘要： A testing method includes the following steps of: accessing a memory chip to put the memory chip into a write leveling mode; inputting a strobe signal into the memory chip under the write leveling mode; adjusting signal edges of the strobe signal to sample a clock state of a clock signal in the memory chip under the write leveling mode; generating a data signal according to the strobe signal under the write leveling mode; and determining types of the memory chip according to the data signal under the write leveling mode.

公开(公告)号：US20240145023A1

公开(公告)日：2024-05-02

申请号：US18341192

申请日：2023-06-26

申请人： Samsung Electronics Co., Ltd.

发明人： Chang-Wook SEO ,  SangYong Yoon ,  Keeho Jung

IPC分类号： G11C29/46 ,  G11C29/12

CPC分类号： G11C29/46 ,  G11C29/1201

摘要： A memory device includes a test mode detector circuit that determines whether the memory device has entered a test mode based on at least one test mode entry signal received through at least one pin of a plurality of pins and generates a test mode detection signal, and a test pad connection circuit that electrically couples a first pin of the plurality of pins to a dedicated test pad of the test mode such that a signal applied to the first pin is transmitted to the dedicated test pad based on the test mode detection signal.