公开(公告)号：US20240224505A1

公开(公告)日：2024-07-04

申请号：US18527091

申请日：2023-12-01

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Ying Rui ,  Silvia Borsari ,  Prashant Raghu ,  Elisabeth Barr ,  Yen Ting Lin ,  Albert P. Chan ,  Martin Chen

IPC: H10B12/00

CPC classification number: H10B12/33 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Digitline structures are formed that are individually directly electrically coupled to the another source/drain regions of multiple of the transistors. The digitline structures individually comprise a conductive digitline and an insulator material thereatop. The insulator material has a top. First insulating material is formed directly above the tops of the insulator material and laterally-over longitudinal sides of the digitline structures and covers across the one source/drain regions laterally-between immediately-adjacent of the digitline structures. Second insulating material is formed over the first insulating material. The second insulating material has a maximum vertical thickness directly above the digitline structures that is greater than its minimum lateral thickness over the longitudinal sides of the digitline structures. The first insulating material is etched through to expose the one source/drain regions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230354585A1

公开(公告)日：2023-11-02

申请号：US17731895

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： Albert P. Chan ,  Sanjeev Sapra ,  Vivek Yadav ,  Yen Ting Lin ,  Devesh Dadhich Shreeram

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10814

Abstract: Methods, apparatuses, and systems related to a digit line and cell contact are described. An example apparatus includes a semiconductor structure comprising a first layer comprising a first material on sidewalls of a plurality of patterned material. The apparatus further includes a second layer comprising a nitride material on sidewalls of the first layer. The apparatus further includes a third layer comprising the first material on sidewalls of the second layer. The apparatus further includes a base area, to provide digit line and cell contact isolation for the semiconductor structure. The apparatus further includes an active area, adjacent to the base area, that is adjacent to the semiconductor structure.