公开(公告)号：US20240389302A1

公开(公告)日：2024-11-21

申请号：US18658787

申请日：2024-05-08

Applicant: Micron Technology, Inc.

Inventor： Jerome A. Imonigie ,  Chia Ying Lin ,  Davide Dorigo ,  Elisabeth Barr ,  Wan Rou Luo ,  Shi Han Wang ,  Sanjeev Sapra ,  Ashwin Panday ,  Vivek Yadav

IPC: H10B12/00

Abstract: Methods, systems, and devices for contact foot wet pullback with liner wet punch are described. A first etching operation may be performed on a stack of materials and a first insulative material to form a plurality of segments including contacts, the contacts formed from a first conductive material of the stack of materials and extending at least partially through the first insulative material. A first liner material may be deposited over the segments and the first insulative material, and a directional gas bias operation may be performed to transform a portion of the first liner material in contact with an extension of the contacts into a second liner material. A second etching operation may be performed to remove the second liner material and expose a surface of the extension, and a third etching operation may be performed remove at least a portion of the extension.

公开(公告)号：US20240224505A1

公开(公告)日：2024-07-04

申请号：US18527091

申请日：2023-12-01

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Ying Rui ,  Silvia Borsari ,  Prashant Raghu ,  Elisabeth Barr ,  Yen Ting Lin ,  Albert P. Chan ,  Martin Chen

IPC: H10B12/00

CPC classification number: H10B12/33 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Digitline structures are formed that are individually directly electrically coupled to the another source/drain regions of multiple of the transistors. The digitline structures individually comprise a conductive digitline and an insulator material thereatop. The insulator material has a top. First insulating material is formed directly above the tops of the insulator material and laterally-over longitudinal sides of the digitline structures and covers across the one source/drain regions laterally-between immediately-adjacent of the digitline structures. Second insulating material is formed over the first insulating material. The second insulating material has a maximum vertical thickness directly above the digitline structures that is greater than its minimum lateral thickness over the longitudinal sides of the digitline structures. The first insulating material is etched through to expose the one source/drain regions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions. Other embodiments, including structure, are disclosed.