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1.发明公开公开(公告)号：US20240365534A1
公开(公告)日：2024-10-31
申请号：US18630435
申请日：2024-04-09
发明人： Huilong ZHU , Tianchun YE , Jun LUO
CPC分类号： H10B12/482 , H10B12/05 , H10B12/485 , H10B12/488 , H10B61/22 , H10N50/10
摘要： A memory device, including: device layers vertically stacked on a substrate, each device layer including an array of active regions of selection transistors, the array including rows in a first direction and columns in a second direction, the active region including a lower source/drain region, a channel portion, and an upper source/drain region; bit lines arranged in the second direction and extending in the first direction along rows; word line layers vertically stacked and corresponding to the device layers, and each including word lines arranged in the first direction and extending in the second direction to at least partially surround a channel portion in a column of a device layer; sub bit lines extending vertically from each bit line and each electrically connected to a lower source/drain region in a row in each device layer above the bit line; and a memory element electrically connected to the upper source/drain region.
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公开(公告)号：US20240357799A1
公开(公告)日：2024-10-24
申请号：US18508833
申请日：2023-11-14
发明人： Choong Hyun LEE , Joon Cheol KIM , Kang-Uk KIM , Jin A KIM , Byoung Wook JANG , Young-Seung CHO
CPC分类号： H10B12/482 , G11C5/063 , H10B12/315 , H10B12/485 , H10B12/488 , H10B12/50
摘要： There is provided a semiconductor memory device capable of improving performance and reliability of an element. The semiconductor memory device includes a substrate including a cell region and a peripheral region, a cell region isolation layer in the substrate, isolating the cell region from the peripheral region, an isolation active region surrounded by the cell region isolation layer, a bit line structure on the cell region, including a cell conductive line and a cell gate electrode in the substrate of the cell region, crossing the cell conductive line.
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公开(公告)号：US12127398B2
公开(公告)日：2024-10-22
申请号：US17448052
申请日：2021-09-19
发明人： Er-Xuan Ping , Zhen Zhou , Lingguo Zhang
IPC分类号： H10B12/00 , H01L21/768 , H01L23/538
CPC分类号： H10B12/485 , H01L21/76841 , H01L21/76877 , H01L23/5384 , H10B12/482
摘要： A method for manufacturing a memory includes the following steps. A substrate and bit line contact layers are provided. Pseudo bit line structures are formed at tops of the bit line contact layers. Sacrificial layers filling regions between adjacent bit line structures are formed, and the sacrificial layers are located on side walls of the pseudo bit line structures and side walls of the bit line contact layers. After forming the sacrificial layers, the pseudo bit line structures are removed to form through holes exposing the bit line contact layers. Bit line conductive parts filling the through holes and covering the bit line contact layers are formed.
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公开(公告)号：US12120868B2
公开(公告)日：2024-10-15
申请号：US17599393
申请日：2021-06-29
发明人： Ran Li , Xing Jin , Ming Cheng
IPC分类号： H01L27/108 , H10B12/00
CPC分类号： H10B12/482 , H10B12/315 , H10B12/488
摘要： A semiconductor device with a buried bit line and a preparation method thereof are provided. The preparation method of a semiconductor device with a buried bit line includes: providing a substrate; forming bit line trenches; forming a bit line structure in the bit line trench; and forming word line structures in the substrate. The semiconductor device with a buried bit line includes a substrate, bit line trenches, a bit line structure, and word line structures.
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公开(公告)号：US20240341089A1
公开(公告)日：2024-10-10
申请号：US18474699
申请日：2023-09-26
发明人： Hosang LEE , Taejin PARK , Hyunjin LEE , Heejae CHAE , Yun CHOI
IPC分类号： H10B12/00
CPC分类号： H10B12/485 , H10B12/02 , H10B12/482
摘要： A semiconductor device according to some example embodiments includes: a substrate that includes an active region between element isolation layers; a word line that overlaps the active region and extends in a first direction; a bit line that overlaps the active region and extends in a second direction crossing the first direction; a buried contact connected to the active region; a first pad between and connecting the active region and the bit line; a second pad between and connecting the active region and the buried contact; and a landing pad connected to the buried contact. Each of the element isolation layers includes a first element isolation layer and a second element isolation layer inside the first element isolation layer, and each of the first pad and the second pad are between the element isolation layers.
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公开(公告)号：US20240341086A1
公开(公告)日：2024-10-10
申请号：US18622473
申请日：2024-03-29
发明人： Yanghee Lee , Jonghyuk Park , Ilyoung Yoon
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/09 , H10B12/50
摘要： An example semiconductor device includes a bit line structure and a bit line capping pattern that are stacked on a memory cell array region. The device further includes a peripheral gate structure including a peripheral gate dielectric layer, a peripheral gate electrode, and a peripheral gate capping pattern that are stacked on a peripheral circuit region. The device further includes a gate spacer on a side surface of the peripheral gate structure, a first peripheral interlayer insulating layer covering the peripheral gate structure and the gate spacer, and a first peripheral contact plug penetrating through the first peripheral interlayer insulating layer. The bit line capping pattern includes a lower bit line capping layer and an upper bit line capping layer that are stacked. A material of the upper bit line capping layer is same as a material of the first peripheral interlayer insulating layer.
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公开(公告)号：US20240339445A1
公开(公告)日：2024-10-10
申请号：US18618645
申请日：2024-03-27
发明人： TOMOHIRO KITANI
CPC分类号： H01L27/0207 , H01L27/0248 , H10B12/50 , H10B12/482
摘要： An apparatus includes: a semiconductor substrate: active regions in the semiconductor substrate, each of the active regions surrounded by a shallow trench isolation and each divided, at least in part, into a first active area and a second active area having a channel area therebetween; first wirings over the plurality of active regions, each of the first wirings coupled to the first active areas of corresponding ones of the active regions; and second wirings over the active regions, each of the second wirings coupled to the second active areas of associated ones of the active regions. Each of the active regions has a longer side in a first direction, each of the first wirings extends in a second direction different from the first direction and each of the second wirings extends in a third direction different from each of the first direction and the second direction.
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公开(公告)号：US12114484B2
公开(公告)日：2024-10-08
申请号：US17650702
申请日：2022-02-11
发明人： Wei Feng , Jingwen Lu , Bingyu Zhu , Zhaopei Cui
IPC分类号： H01L27/108 , H10B12/00
CPC分类号： H10B12/482 , H10B12/30
摘要： The present disclosure provides a method of manufacturing a buried bit line structure and a buried bit line structure. The method of manufacturing a buried bit line structure includes: providing an initial structure, the initial structure including active region structures; forming an initial bit line trench, the initial bit line trench exposing the active region structure; forming a conductive structure, the conductive structure being located at the bottom of the initial bit line trench; forming a bit line contact structure, the bit line contact structure covering the conductive structure, and a top surface of the bit line contact structure being lower than a top surface of the active region structure; and forming an insulation structure, the insulation structure covering the bit line contact structure.
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公开(公告)号：US12113107B2
公开(公告)日：2024-10-08
申请号：US17549328
申请日：2021-12-13
申请人： SK hynix Inc.
发明人： Dae Won Kim , Tae Kyun Kim , Dong Goo Choi
IPC分类号： H01L29/40 , H01L21/311 , H01L21/3213 , H01L21/768 , H10B12/00
CPC分类号： H01L29/401 , H01L21/31144 , H01L21/32139 , H01L21/76834 , H10B12/09 , H10B12/482 , H10B12/485
摘要： A method for fabricating a semiconductor device includes: forming an insulating layer over a substrate including a cell region and a peripheral region; forming an opening in the insulating layer by selectively etching the insulating layer in the cell region; forming a plug conductive layer to fill the opening and cover the insulating film; etching the plug conductive layer and the insulating layer in the peripheral region by using a peri-open mask covering the cell region; trimming the peri-open mask to expose the plug conductive layer in a boundary region where the cell region and the peripheral region contact each other; etching the plug conductive layer in the boundary region by using the trimmed peri-open mask; forming a peri-gate conductive layer over the entire surface of the substrate; and etching the peri-gate conductive layer by using a cell open mask.
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公开(公告)号：US20240334683A1
公开(公告)日：2024-10-03
申请号：US18613525
申请日：2024-03-22
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/02
摘要： Memory devices and methods of manufacturing memory devices are described herein. The memory devices include a bitline metal stack on a surface comprising a matrix of conductive bitline contacts (e.g., polysilicon) and insulating dielectric islands (e.g., silicon nitride (SiN)). The bitline metal stack comprises one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WS), or tungsten silicon nitride (WSiN). The memory devices include a bitline metal layer (e.g., tungsten (W)) on a top surface of the insulating dielectric islands and on the bitline metal stack.
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