公开(公告)号：US20080174924A1

公开(公告)日：2008-07-24

申请号：US11969966

申请日：2008-01-07

申请人： Myoung-Gon KANG ,  Ki-Whan SONG

发明人： Myoung-Gon KANG ,  Ki-Whan SONG

IPC分类号： H02H9/00

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： An electrostatic discharge (ESD) protection device includes an I/O terminal structure and a current discharge structure. The current discharge structure includes a conductive region separated from a bridge region by a gate electrode, a well region formed below the conductive region, another well region separated from the well region by another conductive region, and multiple additional conductive regions implementing dual current discharge paths through another well region.

摘要翻译： 静电放电（ESD）保护装置包括I / O端子结构和电流放电结构。 电流放电结构包括通过栅极电极与桥接区域分离的导电区域，形成在导电区域下方的阱区域，通过另一导电区域与阱区域分离的另一阱区域以及实现双电流放电路径的多个附加导电区域 通过另一个井区。

公开(公告)号：US20080101114A1

公开(公告)日：2008-05-01

申请号：US11781331

申请日：2007-07-23

申请人： Doo-Gon KIM ,  Duk-Ha PARK ,  Myoung-Gon KANG

发明人： Doo-Gon KIM ,  Duk-Ha PARK ,  Myoung-Gon KANG

IPC分类号： G11C11/34

CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

摘要： A semiconductor memory device includes a memory cell array having first and second blocks, respectively including first and second memory cells with floating bodies. The first memory cell is connected between a first bit line and a source line, and the second memory cell is connected between a second bit line and the source line. A sense amplifier equalizes the sense bit line and the inverted sense bit line to be an equalization voltage during an equalization operation, pre-charges the sense bit line and the inverted sense bit line to first and second pre-charge voltages during a pre-charge operation, and amplifies a voltage difference between the sense bit line and the inverted sense bit line during read and write operations. The first pre-charge voltage is higher than the equalization voltage and the second pre-charge voltage is higher than the equalization voltage and lower than the first pre-charge voltage.

摘要翻译： 半导体存储器件包括具有第一和第二块的存储单元阵列，分别包括具有浮体的第一和第二存储单元。 第一存储单元连接在第一位线和源极线之间，第二存储单元连接在第二位线和源极线之间。 在均衡操作期间，感测放大器将感测位线和反相感测位线均衡为均衡电压，在预充电期间将感测位线和反相检测位线预充电到第一和第二预充电电压 并且在读取和写入操作期间放大感测位线和反相读取位线之间的电压差。 第一预充电电压高于均衡电压，第二预充电电压高于均衡电压并低于第一预充电电压。