公开(公告)号：US07933154B2

公开(公告)日：2011-04-26

申请号：US12213937

申请日：2008-06-26

申请人： Myoung Gon Kang ,  Ki Tae Park ,  Doo Gon Kim ,  Yeong Taek Lee

发明人： Myoung Gon Kang ,  Ki Tae Park ,  Doo Gon Kim ,  Yeong Taek Lee

IPC分类号： G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

摘要： A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n−1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder.

摘要翻译： 非易失性存储器件包括存储单元阵列，经由多个位线从其读取数据，存储单元阵列包括具有分别与多个字线连接的门的多个存储器单元，第一类型全局字线解码器，被配置为选择性地施加n 不同的电压，其中n是大于或等于3的整数，与程序模式中的多个字线的相应字线相对应，并且第二类型全局字线解码器被配置为选择性地将（n-1）个不同的电压应用于相应的 在编程模式下的多个字线的字线，第二类全局字线解码器具有比第一类全局字线解码器少的开关元件。

公开(公告)号：US20100046290A1

公开(公告)日：2010-02-25

申请号：US12509611

申请日：2009-07-27

申请人： Ki-Tae PARK ,  Myoung Gon KANG

发明人： Ki-Tae PARK ,  Myoung Gon KANG

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A flash memory device includes a first switch connecting one of a first cell string and a second cell string to a first bit line selectively, a second switch connecting the second cell string to a second bit line, and a control logic circuit providing bias voltages to the first and second cell strings through the first and second bit lines respectively and controlling the first and second cell stings to be simultaneously programmed.

摘要翻译： 闪速存储器件包括：将第一单元串和第二单元串之一选择性地连接到第一位线的第一开关，将第二单元串连接到第二位线的第二开关以及将偏置电压提供给 分别通过第一和第二位线的第一和第二单元串，并且控制第一和第二单元电池脚被同时编程。

公开(公告)号：US08300463B2

公开(公告)日：2012-10-30

申请号：US12726408

申请日：2010-03-18

申请人： Ki Tae Park ,  Myoung Gon Kang

发明人： Ki Tae Park ,  Myoung Gon Kang

IPC分类号： G11C16/04 ,  G11C16/06 ,  G06F13/00

CPC分类号： G11C16/349 ,  G11C16/10 ,  G11C16/3495

摘要： A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block.

摘要翻译： 非易失性存储器件包括存储单元阵列，该存储单元阵列包括分成多个区域的多个存储块，以及控制逻辑元件。 控制逻辑部件基于存储器块的编程/擦除周期选择要编程的存储器块，并且选择用于对所选存储器块的区域进行编程的程序规则。

公开(公告)号：US08144517B2

公开(公告)日：2012-03-27

申请号：US12472033

申请日：2009-05-26

申请人： Doo Gon Kim ,  Ki Tae Park ,  Myoung Gon Kang

发明人： Doo Gon Kim ,  Ki Tae Park ,  Myoung Gon Kang

IPC分类号： G11C16/04

CPC分类号： G11C11/5621 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454

摘要： A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix, and the control parameters for each group are responsive to the stored characteristics for that group; the method including organizing memory cells into groups, storing characteristics for each group in a look-up matrix, providing control parameters for each of the groups, where the control parameters for each group are responsive to its stored characteristics, and driving each memory cell in accordance with its provided control parameters.

摘要翻译： 提供了一种用于多层非易失性半导体存储器的自适应控制的方法和装置，该装置包括组织成组的存储单元和具有查找矩阵的控制电路，用于为存储每个组的特性的组中的每个组提供控制参数 在查找矩阵中，并且每个组的控制参数响应于该组的存储特性; 所述方法包括将存储器单元组合成组，将查找矩阵中的每个组存储特性，为每个组提供控制参数，其中每个组的控制参数响应于其存储的特性，以及驱动每个存储单元 根据其提供的控制参数。

公开(公告)号：US07539041B2

公开(公告)日：2009-05-26

申请号：US11781331

申请日：2007-07-23

申请人： Doo-Gon Kim ,  Duk-Ha Park ,  Myoung-Gon Kang

发明人： Doo-Gon Kim ,  Duk-Ha Park ,  Myoung-Gon Kang

IPC分类号： G11C11/24

CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

摘要： A semiconductor memory device includes a memory cell array having first and second blocks, respectively including first and second memory cells with floating bodies. The first memory cell is connected between a first bit line and a source line, and the second memory cell is connected between a second bit line and the source line. A sense amplifier equalizes the sense bit line and the inverted sense bit line to be an equalization voltage during an equalization operation, pre-charges the sense bit line and the inverted sense bit line to first and second pre-charge voltages during a pre-charge operation, and amplifies a voltage difference between the sense bit line and the inverted sense bit line during read and write operations. The first pre-charge voltage is higher than the equalization voltage and the second pre-charge voltage is higher than the equalization voltage and lower than the first pre-charge voltage.

摘要翻译： 半导体存储器件包括具有第一和第二块的存储单元阵列，分别包括具有浮体的第一和第二存储单元。 第一存储单元连接在第一位线和源极线之间，第二存储单元连接在第二位线和源极线之间。 在均衡操作期间，感测放大器将感测位线和反相感测位线均衡为均衡电压，在预充电期间将感测位线和反相检测位线预充电到第一和第二预充电电压 并且在读取和写入操作期间放大感测位线和反相感测位线之间的电压差。 第一预充电电压高于均衡电压，第二预充电电压高于均衡电压并低于第一预充电电压。

公开(公告)号：US08089811B2

公开(公告)日：2012-01-03

申请号：US12580949

申请日：2009-10-16

申请人： Myoung Gon Kang ,  Kitae Park

发明人： Myoung Gon Kang ,  Kitae Park

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427 ,  H01L27/11521 ,  H01L27/11524

摘要： Flash memory devices include a first memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to a bit line and a second memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to the bit line. The first dummy memory cells of the first and second memory cell strings have gates connected in common to a first dummy word line and have different threshold voltages and the second dummy memory cells of the first and second memory cell strings have gates connected in common to a second dummy bit line and have different threshold voltages. In some embodiments, the first dummy memory cell of the first memory cell string and the second dummy memory cell of the second memory cell string may have threshold voltages greater than a predetermined voltage and the second dummy memory cell of the first memory cell string and the first dummy memory cell of the second memory cell string may have threshold voltages less than the predetermined voltage.

摘要翻译： 闪速存储器件包括包括多个串联存储器单元的第一存储器单元串和被配置为将串联连接的存储单元耦合到位线的第一和第二串联虚拟晶体管，以及包括多个 串联连接的存储器单元和被配置为将串联连接的存储器单元耦合到位线的第一和第二串联连接的虚拟晶体管。 第一和第二存储单元串的第一虚拟存储单元具有共同连接到第一虚拟字线并具有不同阈值电压的栅极，并且第一和第二存储单元串的第二虚拟存储单元具有共同连接到 第二虚位线并具有不同的阈值电压。 在一些实施例中，第一存储单元串的第一虚拟存储单元和第二存储单元串的第二空存储单元可以具有大于预定电压的阈值电压，并且第一存储单元串的第二空存储单元和 第二存储单元串的第一虚拟存储单元可以具有小于预定电压的阈值电压。

公开(公告)号：US20100246266A1

公开(公告)日：2010-09-30

申请号：US12726408

申请日：2010-03-18

申请人： Ki Tae PARK ,  Myoung Gon KANG

发明人： Ki Tae PARK ,  Myoung Gon KANG

IPC分类号： G11C16/04

CPC分类号： G11C16/349 ,  G11C16/10 ,  G11C16/3495

摘要： A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block.

摘要翻译： 非易失性存储器件包括存储单元阵列，该存储单元阵列包括分成多个区域的多个存储块，以及控制逻辑元件。 控制逻辑部件基于存储器块的编程/擦除周期来选择要编程的存储器块，并且选择用于对所选存储器块的区域进行编程的程序规则。

公开(公告)号：US20100039861A1

公开(公告)日：2010-02-18

申请号：US12506345

申请日：2009-07-21

申请人： Kitae Park ,  Myoung Gon Kang

发明人： Kitae Park ,  Myoung Gon Kang

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

摘要： Disclosed is a nonvolatile memory including a memory cell array including a first cell string connected between a first bit line and a first common source line, and a second cell string a second common source line and a second bit line adjacent to the first bit line. The nonvolatile memory also includes a control logic circuit configured to independently control the first and second common source lines.

摘要翻译： 公开了一种非易失性存储器，包括存储单元阵列，其包括连接在第一位线和第一公共源极线之间的第一单元串，以及第二单元串，与第一位线相邻的第二公共源极线和第二位线。 非易失性存储器还包括被配置为独立地控制第一和第二公共源极线的控制逻辑电路。

公开(公告)号：US20090003067A1

公开(公告)日：2009-01-01

申请号：US12213937

申请日：2008-06-26

申请人： Myoung Gon Kang ,  Ki Tae Park ,  Dao Gon Kim ,  Yeong Taek Lee

发明人： Myoung Gon Kang ,  Ki Tae Park ,  Dao Gon Kim ,  Yeong Taek Lee

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

摘要： A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n−1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder.

摘要翻译： 非易失性存储器件包括存储单元阵列，经由多个位线从其读取数据，存储单元阵列包括具有分别与多个字线连接的门的多个存储器单元，第一类型全局字线解码器，被配置为选择性地施加n 不同的电压，其中n是大于或等于3的整数，与程序模式中的多个字线的相应字线相对应，并且第二类型全局字线解码器被配置为选择性地将（n-1）个不同的电压应用于相应的 在编程模式下的多个字线的字线，第二类全局字线解码器具有比第一类全局字线解码器少的开关元件。

公开(公告)号：US08154924B2

公开(公告)日：2012-04-10

申请号：US12506345

申请日：2009-07-21

申请人： Kitae Park ,  Myoung Gon Kang

发明人： Kitae Park ,  Myoung Gon Kang

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

摘要： Disclosed is a nonvolatile memory including a memory cell array including a first cell string connected between a first bit line and a first common source line, and a second cell string a second common source line and a second bit line adjacent to the first bit line. The nonvolatile memory also includes a control logic circuit configured to independently control the first and second common source lines.

摘要翻译： 公开了一种非易失性存储器，包括存储单元阵列，其包括连接在第一位线和第一公共源极线之间的第一单元串，以及第二单元串，与第一位线相邻的第二公共源极线和第二位线。 非易失性存储器还包括被配置为独立地控制第一和第二公共源极线的控制逻辑电路。