公开(公告)号：US08861264B2

公开(公告)日：2014-10-14

申请号：US13178993

申请日：2011-07-08

申请人： Ick Hyun Song ,  Ki Whan Song ,  Jin-Young Kim

发明人： Ick Hyun Song ,  Ki Whan Song ,  Jin-Young Kim

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C8/08 ,  G11C7/12

CPC分类号： G11C7/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/004

摘要： A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first pre-charge circuit located between a plurality of sub arrays included in a memory cell array and pre-charging the first global bit line with a second pre-charge voltage by using a second pre-charge circuit located outside the memory cell array.

摘要翻译： 提供了一种预充电控制方法和装置。 预充电控制方法包括通过使用位于存储单元阵列中包括的多个子阵列之间的至少第一预充电电路来对具有第一预充电电压的第一全局位线进行预充电，并对 通过使用位于存储单元阵列外部的第二预充电电路，具有第二预充电电压的第一全局位线。

公开(公告)号：US08054693B2

公开(公告)日：2011-11-08

申请号：US12654283

申请日：2009-12-16

申请人： Ki-Whan Song ,  Nam-Kyun Tak

发明人： Ki-Whan Song ,  Nam-Kyun Tak

IPC分类号： G11C16/04

CPC分类号： G11C11/404 ,  G11C11/4076 ,  G11C2211/4016

摘要： In example embodiments, the semiconductor memory device, and the method for operating the semiconductor memory device, includes a memory cell array having a plurality of memory cells each formed of a transistor having a floating body. The transistors are coupled between a plurality of word lines, a plurality of source lines and a plurality of bit lines. Additionally, the memory cell array includes a controller configured to read data from at least one of the memory cells and restore data to the memory cell storing a first data state through a bit operation of the memory cell. The controller restores data to the memory cell by applying a first source-line control voltage to a selected source line and applying a first word-line control voltage to a selected word line in a first period of a read operation. Also, the controller is configured to restore data to the memory cell, which is storing a second data state, by applying a second source-line control voltage to the selected source line and applying a second word-line control voltage to the selected word line in a second period of the read operation.

摘要翻译： 在示例实施例中，半导体存储器件以及用于操作半导体存储器件的方法包括具有多个存储单元的存储单元阵列，每个存储单元均由具有浮体的晶体管形成。 晶体管耦合在多个字线，多条源极线和多个位线之间。 此外，存储单元阵列包括控制器，其被配置为从存储器单元中的至少一个读取数据，并且通过存储器单元的位操作将数据恢复到存储第一数据状态的存储单元。 控制器通过对所选择的源极线施加第一源极线控制电压并且在读取操作的第一周期中对所选择的字线施加第一字线控制电压来将数据恢复到存储器单元。 此外，控制器被配置为通过对所选择的源极线施加第二源极线控制电压并将第二字线控制电压施加到所选择的字线来将数据恢复到存储第二数据状态的存储器单元 在读操作的第二周期。

公开(公告)号：US08009488B2

公开(公告)日：2011-08-30

申请号：US12385198

申请日：2009-04-01

申请人： Duk-Ha Park ,  Ki-Whan Song

发明人： Duk-Ha Park ,  Ki-Whan Song

IPC分类号： G11C7/02 ,  G11C7/06

CPC分类号： G11C11/404 ,  G11C11/4076 ,  G11C11/4099 ,  G11C2211/4016

摘要： A semiconductor memory device includes a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array including memory cells each having a transistor with a floating body, a reference voltage generator configured to have a reference memory cell and generate a reference voltage for bit line sensing corresponding to a current flowing into a reference memory cell during a data read operation, first and second prechargers configured to precharge a bit line connected to non-selected memory cells to the reference voltage in response to first and second precharge control signals during the data read operation, and a sense amplifier configured to sense and amplify a voltage difference between a bit line connected to the selected memory cells and a bit line connected to the non-selected memory cells during the data read operation.

摘要翻译： 半导体存储器件包括连接到字线，源极线和位线的多个存储单元阵列块，每个存储单元阵列包括每个具有带有浮体的晶体管的存储单元，参考电压发生器被配置为具有参考存储器 并且在数据读取操作期间产生与流入参考存储单元的电流相对应的位线检测的参考电压，第一和第二预充电器被配置为响应于第一和第二预充电器将连接到未选择存储单元的位线预充电到参考电压 数据读取操作期间的第一和第二预充电控制信号;以及读出放大器，被配置为在数据读取期间感测和放大连接到所选择的存储器单元的位线与连接到未选择存储单元的位线之间的电压差 操作。

公开(公告)号：US07944759B2

公开(公告)日：2011-05-17

申请号：US12285520

申请日：2008-10-08

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： G11C16/04

CPC分类号： G11C5/147 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cells having a transistor with a floating body, a source line driver configured to control the source lines to select the memory cells in response to an address signal, a source line voltage generation unit configured to generate a source line target voltage, receive an source line output voltage from the source line driver, compare the level of the source line output voltage with the level of the source line target voltage, generate a source line voltage of which the level is adaptively varied according to a temperature, and a sense amplifier configured to sense a difference in current flowing through the bit lines in response to data read from a selected memory cell, amplify the difference to a level having high output driving capability and output the amplified current.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括具有浮置体的晶体管的多个存储器单元，源极线驱动器，被配置为响应于地址信号控制源极线选择存储单元，源极线电压产生 被配置为产生源极线路目标电压的单元，从源极线驱动器接收源极线路输出电压，将源极线路输出电压的电平与源极线路目标电压的电平进行比较，生成源极线电压， 根据温度自适应地变化;以及读出放大器，被配置为响应于从选择的存储单元读取的数据来感测流过位线的电流差，将该差放大到具有高输出驱动能力的电平，并输出放大的 当前。

公开(公告)号：US07906397B2

公开(公告)日：2011-03-15

申请号：US12410010

申请日：2009-03-24

申请人： Ki-whan Song ,  Byung-Gook Park

发明人： Ki-whan Song ,  Byung-Gook Park

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.

摘要翻译： 非易失性半导体存储器件包括从半导体衬底向上突出并具有相应顶表面和相对侧壁的多个柱，在柱的顶表面上的位线，并沿着第一方向连接一排柱，一对 在多个柱中的一个柱的相对的侧壁上并且在位线下方交叉的字线以及插入在该对字线中的相应一个字线和多个柱之一之间的一对存储层。 制造非易失性半导体存储器件的方法包括选择性地蚀刻半导体衬底以形成具有相对侧壁并沿着方向布置的多个条纹，沿着条纹的侧壁形成存储层和字线，选择性地蚀刻条纹以形成多个 并且形成连接柱子并跨越字线上方的位线。

公开(公告)号：US20110042746A1

公开(公告)日：2011-02-24

申请号：US12940304

申请日：2010-11-05

申请人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

发明人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

IPC分类号： H01L29/772

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/7834 ,  H01L29/7841

摘要： A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

摘要翻译： 单晶体管浮体动态随机存取存储器（DRAM）器件包括位于半导体衬底上的浮体和位于浮体上的栅电极，浮体包括过剩的载流子存储区。 DRAM器件还包括分别位于栅极两侧的源极和漏极区域以及位于浮体与源极和漏极区域之间的泄漏屏蔽图案。 源极和漏极区域中的每一个接触可以位于源极和漏极区域之间的浮体。 浮体还可以横向延伸在泄漏屏蔽图案下方，这可以布置在栅电极的外侧。

公开(公告)号：US20110013469A1

公开(公告)日：2011-01-20

申请号：US12662644

申请日：2010-04-27

申请人： Duk-Ha Park ,  Ki-Whan Song

发明人： Duk-Ha Park ,  Ki-Whan Song

IPC分类号： G11C29/00 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18 ,  G11C29/785

摘要： A redundancy circuit includes at least one fuse set circuit and a fuse control circuit. The at least one fuse set circuit includes a plurality of fuse cells, each of the plurality of fuse cells having a first transistor and a second transistor having same sizes. The first transistor has a first contact resistance and the second transistor has a second contact resistance different from the first contact resistance. Each of the plurality of fuse cells stores a fuse address indicating a defective cell in a repair operation and outputs a repair address corresponding to the stored fuse address. The fuse control circuit, connected to the plurality of fuse cells, controls the plurality of fuse cells in response to a program signal and a precharge signal such that the corresponding fuse address is stored in each of the fuse cells.

摘要翻译： 冗余电路包括至少一个熔丝组电路和熔丝控制电路。 所述至少一个熔丝组电路包括多个熔丝单元，所述多个熔丝单元中的每一个具有第一晶体管和具有相同尺寸的第二晶体管。 第一晶体管具有第一接触电阻，第二晶体管具有不同于第一接触电阻的第二接触电阻。 多个熔丝单元中的每一个在修复操作中存储指示有缺陷单元的熔丝地址，并输出对应于所存储的熔丝地址的修复地址。 连接到多个熔丝单元的熔丝控制电路响应于编程信号和预充电信号控制多个熔丝单元，使得相应的熔丝地址存储在每个熔丝单元中。

公开(公告)号：US07843750B2

公开(公告)日：2010-11-30

申请号：US11797867

申请日：2007-05-08

申请人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

发明人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

IPC分类号： G11C7/00

CPC分类号： H01L27/10876 ,  G11C7/1042 ,  G11C7/12 ,  G11C11/404 ,  G11C11/4094 ,  H01L29/78 ,  H01L29/7827

摘要： A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line.

摘要翻译： 提供一种包括具有垂直沟道结构的晶体管的半导体存储器件。 该器件包括第一子存储单元阵列，该第一子存储单元阵列包括连接到第一位线并包括具有垂直沟道结构的晶体管的第一存储单元，第二子存储单元阵列，包括连接到第一反相位线的第二存储单元， 具有垂直沟道结构的晶体管和多个预充电块。 此外，第一和第二预充电块设置在第一位线的第一和第二侧并对第一位线进行预充电，并且第三和第四预充电块设置在第一反相位线的第一和第二侧，并且对第一 反转位线。

公开(公告)号：US20100118616A1

公开(公告)日：2010-05-13

申请号：US12591176

申请日：2009-11-12

申请人： Hoe-Ju Chung ,  Ki-Whan Song

发明人： Hoe-Ju Chung ,  Ki-Whan Song

IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C8/10

CPC分类号： G11C7/06 ,  G11C7/1012 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/005

摘要： A semiconductor memory device having shared sense amplifiers is provided. The semiconductor memory device has a bit-line selector disposed closer to a memory cell array than a column decoder. When the column decoder outputs a bit-line indication signal corresponding to the number of bit lines, the bit-line selector selects a plurality of bit lines in response to the bit-line indication signal. Thus, it is possible to reduce the number of signals output from the column decoder.

摘要翻译： 提供了具有共享读出放大器的半导体存储器件。 半导体存储器件具有比列解码器更靠近存储单元阵列设置的位线选择器。 当列解码器输出与位线数相对应的位线指示信号时，位线选择器响应于位线指示信号选择多个位线。 因此，可以减少从列解码器输出的信号的数量。

公开(公告)号：US20090278194A1

公开(公告)日：2009-11-12

申请号：US12453036

申请日：2009-04-28

申请人： Nam-Kyun Tak ,  Ki-Whan Song

发明人： Nam-Kyun Tak ,  Ki-Whan Song

IPC分类号： H01L29/792 ,  H01L29/786

CPC分类号： H01L29/7841 ,  H01L29/785

摘要： A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain region and a floating body formed between the source region and the drain region, and a gate pattern formed on the floating body, wherein the floating body includes a main floating body having the same top surface height as one of the source region and the drain region, and a first upper floating body formed between the main floating body and the gate pattern.

摘要翻译： 提供其数据存储能力增加并且漏电流减小的无电容器一晶体管（1T）半导体器件。 电容器1T半导体器件包括形成在基板上的掩埋绝缘层，形成在掩埋绝缘层上的有源区，并且包括源区域，漏极区域和形成在源极区域与漏极区域之间的浮体，以及 形成在所述浮体上的栅极图案，其中所述浮体包括具有与所述源极区域和所述漏极区域中的一个相同的顶部高度的主浮动体，以及形成在所述主浮体和所述栅极之间的第一上浮体 模式。