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公开(公告)号：US11695377B2
公开(公告)日：2023-07-04
申请号：US17501757
申请日：2021-10-14
Applicant: NXP B.V.
Inventor： Robert van Veldhoven , John Pigott
CPC classification number: H03F3/387 , H03F3/1935 , H03F3/45179 , H03F3/45183
Abstract: An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.
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Patent Agency Ranking
公开(公告)号：US10958151B2
公开(公告)日：2021-03-23
申请号：US16803084
申请日：2020-02-27
Applicant: NXP B.V.
Inventor： Mojtaba Ashourloo , Venkata Raghuram Namburi , Gerard Villar Piqué , John Pigott , Olivier Trescases , Hendrik Bergveld , Alaa Eldin Y El Sherif
Abstract: Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.
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公开(公告)号：US20200326384A1
公开(公告)日：2020-10-15
申请号：US16813849
申请日：2020-03-10
Applicant: NXP B.V.
Inventor： Mojtaba Ashourloo , Venkata Raghuram Namburi , Gerard Villar Piqué , John Pigott , Olivier Trescases , Hendrik Bergveld , Alaa Eldin Y. El Sherif
Abstract: There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw1, Vsw2, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw1[n−1], Vsw2[n−1]) and in a next subsequent operating cycle (Vsw1[n], Vsw2[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.
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公开(公告)号：US20230118374A1
公开(公告)日：2023-04-20
申请号：US17501757
申请日：2021-10-14
Applicant: NXP B.V.
Inventor： Robert van Veldhoven , John Pigott
IPC: H03F3/387
Abstract: An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.
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公开(公告)号：US11293992B2
公开(公告)日：2022-04-05
申请号：US16813849
申请日：2020-03-10
Applicant: NXP B.V.
Inventor： Mojtaba Ashourloo , Venkata Raghuram Namburi , Gerard Villar Piqué , John Pigott , Olivier Trescases , Hendrik Bergveld , Alaa Eldin Y El Sherif
Abstract: There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw1, Vsw2, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw1[n−1], Vsw2[n−1]) and in a next subsequent operating cycle (Vsw1[n], Vsw2[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.
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公开(公告)号：US20200295649A1
公开(公告)日：2020-09-17
申请号：US16803084
申请日：2020-02-27
Applicant: NXP B.V.
Inventor： Mojtaba Ashourloo , Venkata Raghuram Namburi , Gerard Villar Piqué , John Pigott , Olivier Trescases , Hendrik Bergveld , Alaa Eldin Y. El Sherif
Abstract: Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.
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