公开(公告)号：US08963586B2

公开(公告)日：2015-02-24

申请号：US14172256

申请日：2014-02-04

Applicant: NXP B.V.

Inventor： Mustafa Acar ,  Katarzyna Nowak

IPC: H03K3/00 ,  H03B1/00 ,  H03K19/0185 ,  H03K19/003

CPC classification number: H03K19/018521 ,  H03K19/00315 ,  H03K19/018528

Abstract: A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.

Abstract translation: 功率级具有由一个或多个缓冲级4驱动的差分输出级2.缓冲级4被实现为高侧缓冲器12和低侧缓冲器12,14，每个缓冲器本身都是使用形成在隔离级中的晶体管实现的差分缓冲器， 良好的技术，如三阱CMOS。

公开(公告)号：US20140152353A1

公开(公告)日：2014-06-05

申请号：US14172256

申请日：2014-02-04

Applicant: NXP B.V.

Inventor： Mustafa Acar ,  Katarzyna Nowak

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K19/00315 ,  H03K19/018528

Abstract: A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.

Abstract translation: 功率级具有由一个或多个缓冲级4驱动的差分输出级2.缓冲级4被实现为高侧缓冲器12和低侧缓冲器12,14，每个缓冲器本身都是使用形成在隔离级中的晶体管实现的差分缓冲器， 良好的技术，如三阱CMOS。

公开(公告)号：US08692591B2

公开(公告)日：2014-04-08

申请号：US13661275

申请日：2012-10-26

Applicant: NXP B.V.

Inventor： Mustafa Acar ,  Katarzyna Nowak

IPC: H03K3/00

CPC classification number: H03K19/018521 ,  H03K19/00315 ,  H03K19/018528

Abstract: A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.

Abstract translation: 功率级具有由一个或多个缓冲级4驱动的差分输出级2.缓冲级4被实现为高侧缓冲器12和低侧缓冲器12,14，每个缓冲器本身都是使用形成在隔离级中的晶体管实现的差分缓冲器， 良好的技术，如三阱CMOS。

公开(公告)号：US20130285713A1

公开(公告)日：2013-10-31

申请号：US13661275

申请日：2012-10-26

Applicant: NXP B.V.

Inventor： Mustafa Acar ,  Katarzyna Nowak

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K19/00315 ,  H03K19/018528

Abstract: A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.

Abstract translation: 功率级具有由一个或多个缓冲级4驱动的差分输出级2.缓冲级4被实现为高侧缓冲器12和低侧缓冲器12,14，每个缓冲器本身都是使用形成在隔离级中的晶体管实现的差分缓冲器， 良好的技术，如三阱CMOS。