Fully digital glitch detection mechanism with process and temperature compensation

    公开(公告)号:US11355457B2

    公开(公告)日:2022-06-07

    申请号:US16445650

    申请日:2019-06-19

    Applicant: NXP B.V.

    Abstract: A fully digital method and apparatus are provided for detecting glitches on a monitored line by providing a toggle signal to an initial delay circuit and a plurality of delay elements formed with standard logic cells so that logic values from the delay elements are captured in a corresponding plurality of clocked capture flops to provide a digitized representation of a delay value during a sampling period which is converted to a numerical measurement result which is evaluated against a reference value to generate an output error signal if a difference between the numerical measurement result and reference value exceeds a programmable margin, where the initial delay circuit is configured with a trim setting to impose an initial delay to compensate for process variations and where the reference value is adapted over a plurality of sampling periods to compensate for temperature effects on the numerical measurement result.

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