Simultaneous simulation of multiple blocks using efficient packet communication to emulate inter-block buses

    公开(公告)号:US09727673B1

    公开(公告)日:2017-08-08

    申请号:US14885978

    申请日:2015-10-16

    CPC classification number: G06F17/5009 G06F17/5022 G06F17/5081 G06F2217/04

    Abstract: An integrated circuit includes a first circuit, a second circuit, and a bus that couples the circuits together. The first circuit is simulated on a first simulator at the same time that the second circuit is simulated on a second simulator. A simulator plug-in is incorporated into the simulation model of the first circuit. A simulator plug-in is incorporated into the simulation model of the second circuit. If valid data is to pass from the first to second circuit across the bus during simulation, then the plug-in of the first model causes a network stack to generate a packet. The packet carries the data. After communication to the second simulator, the data is recovered from the packet, and is injected by the plug-in of the second model into the simulation of the second circuit. By exchanging data back and forth this way, multiple circuits are simulated simultaneously on different simulators.

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