公开(公告)号：US09013948B2

公开(公告)日：2015-04-21

申请号：US14181162

申请日：2014-02-14

Applicant: Novatek Microelectronics Corp.

Inventor： Ching-Wen Lai ,  Hsi-Chi Ho

IPC: G11C8/00 ,  G11C11/406 ,  G11C8/12 ,  G11C8/18

CPC classification number: G11C11/40603 ,  G11C8/12 ,  G11C8/18

Abstract: A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters.

Abstract translation: 提供了一种用于显示装置的存储器架构及其控制方法。 存储器架构包括显示数据存储器和存储器控制器。 显示数据存储器包括N个子存储器和N×M个仲裁器，其中N是正整数，M是等于或大于2的正整数。每个子存储器包括由地址分割的M个存储器块。 每个M仲裁器耦合到每个子存储器的M个存储器块。 耦合到N×M仲裁器的存储器控​​制器根据输入请求信号和输入地址信号的集合生成N×M组请求信号并输出​​地址信号，并且向N×M仲裁器发送顺序控制 N×M仲裁者。