公开(公告)号：US20170300105A1

公开(公告)日：2017-10-19

申请号：US15635185

申请日：2017-06-27

Applicant: NOVATEK Microelectronics Corp.

Inventor： Kuei-Chung Chang ,  Feng-Jung Kuo ,  Hsi-Chi Ho

IPC: G06F1/32 ,  G06T1/60 ,  G09G3/36

CPC classification number: G06F1/3265 ,  G06T1/60 ,  G09G3/36 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2360/02 ,  Y02D10/153

Abstract: A drive circuit applicable to a display device includes a first signal path and a second signal path. The first signal path, configured to receive image data and transmit the image data in a first operation mode, includes a compression unit, a storage unit and a de-compression unit. In the first operation mode, the compression unit performs a compression procedure on the image data to generate compression data, the storage unit stores the compression data, and the de-compression unit receives the compression data and performs a de-compression procedure on the compression data to recover the image data. The second signal path is configured to receive image data, transmit the image data to the storage unit so as to bypass the compression unit, and transmit the image data received from the storage unit to a display unit so as to bypass the decompression unit in a second operation mode.

公开(公告)号：US08681086B2

公开(公告)日：2014-03-25

申请号：US13722326

申请日：2012-12-20

Applicant: Novatek Microelectronics Corp.

Inventor： Yu-Hsun Peng ,  Hsi-Chi Ho ,  Li-Chun Huang

IPC: G09G3/36

CPC classification number: G09G5/00 ,  G09G3/3688 ,  G09G2310/0289 ,  G09G2310/0297

Abstract: A data driver includes two data processing circuits for respectively providing positive and negative pixel voltages according to first and second pixel data, and a multiplexer circuit including multiplexer units. Each multiplexer unit has first and second input terminals respectively receiving the positive and negative pixel voltages, and an output terminal coupled to a data line. A first switching device has first and second switches serially coupled between the first input and output terminals. A node between the first and second switches is selectively grounded via a third switch. A second switching device has fourth and fifth switches serially coupled between the second input and output terminals. A node between the fourth and fifth switches is selectively grounded via a sixth switch. When the first and second switches turn on, the sixth switch turns on. When the fourth and fifth switches turn on, the third switch turns on.

Abstract translation: 数据驱动器包括用于分别根据第一和第二像素数据提供正和负像素电压的两个数据处理电路，以及包括多路复用器单元的多路复用器电路。 每个多路复用器单元具有分别接收正像素电压和负像素电压的第一和第二输入端子以及耦合到数据线的输出端子。 第一开关装置具有串联耦合在第一输入端和输出端之间的第一和第二开关。 第一和第二开关之间的节点经由第三开关选择性接地。 第二开关器件具有串联耦合在第二输入和输出端子之间的第四和第五开关。 第四开关和第五开关之间的节点通过第六开关选择性接地。 当第一和第二开关导通时，第六开关导通。 当第四和第五开关导通时，第三开关导通。

公开(公告)号：US10534422B2

公开(公告)日：2020-01-14

申请号：US16021041

申请日：2018-06-28

Applicant: NOVATEK Microelectronics Corp.

Inventor： Kuei-Chung Chang ,  Feng-Jung Kuo ,  Hsi-Chi Ho

IPC: G06F1/3234 ,  G06T1/60 ,  G09G3/36

Abstract: A drive circuit applicable to a display device includes a first signal path and a second signal path. The first signal path, configured to receive and transmit image data, includes a compression unit configured to perform a compression procedure on the image data to generate compression data; a storage unit configured to store the compression data; and a de-compression unit configured to perform a de-compression procedure on the compression data to recover the image data. The second signal path is configured to transmit the image data to the storage unit so as to bypass the compression unit, and transmit the image data received from the storage unit to a display unit so as to bypass the de-compression unit when the image data is not transmitted by the first signal path. The received image data is passed through the first signal path or the second signal path depending upon its characteristics.

公开(公告)号：US09013948B2

公开(公告)日：2015-04-21

申请号：US14181162

申请日：2014-02-14

Applicant: Novatek Microelectronics Corp.

Inventor： Ching-Wen Lai ,  Hsi-Chi Ho

IPC: G11C8/00 ,  G11C11/406 ,  G11C8/12 ,  G11C8/18

CPC classification number: G11C11/40603 ,  G11C8/12 ,  G11C8/18

Abstract: A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters.

Abstract translation: 提供了一种用于显示装置的存储器架构及其控制方法。 存储器架构包括显示数据存储器和存储器控制器。 显示数据存储器包括N个子存储器和N×M个仲裁器，其中N是正整数，M是等于或大于2的正整数。每个子存储器包括由地址分割的M个存储器块。 每个M仲裁器耦合到每个子存储器的M个存储器块。 耦合到N×M仲裁器的存储器控​​制器根据输入请求信号和输入地址信号的集合生成N×M组请求信号并输出​​地址信号，并且向N×M仲裁器发送顺序控制 N×M仲裁者。

公开(公告)号：US10042411B2

公开(公告)日：2018-08-07

申请号：US15635185

申请日：2017-06-27

Applicant: NOVATEK Microelectronics Corp.

Inventor： Kuei-Chung Chang ,  Feng-Jung Kuo ,  Hsi-Chi Ho

IPC: G06F1/32 ,  G09G3/36 ,  G06T1/60

Abstract: A drive circuit applicable to a display device includes a first signal path and a second signal path. The first signal path, configured to receive image data and transmit the image data in a first operation mode, includes a compression unit, a storage unit and a de-compression unit. In the first operation mode, the compression unit performs a compression procedure on the image data to generate compression data, the storage unit stores the compression data, and the de-compression unit receives the compression data and performs a de-compression procedure on the compression data to recover the image data. The second signal path is configured to receive image data, transmit the image data to the storage unit so as to bypass the compression unit, and transmit the image data received from the storage unit to a display unit so as to bypass the decompression unit in a second operation mode.

公开(公告)号：US09727120B2

公开(公告)日：2017-08-08

申请号：US14078490

申请日：2013-11-12

Applicant: NOVATEK Microelectronics Corp.

Inventor： Kuei-Chung Chang ,  Feng-Jung Kuo ,  Hsi-Chi Ho

IPC: G06T1/60 ,  G06F1/32

CPC classification number: G06F1/3265 ,  G06T1/60 ,  G09G3/36 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2360/02 ,  Y02D10/153

Abstract: A data compression system for a liquid crystal display (LCD) includes a host and a drive circuit. The host is utilized for outputting image data in a first data format or a second data format according to an operation mode of the LCD. The drive circuit includes a bypass path, for transmitting the image data according to the operation mode; a compression unit, coupled to the host, for receiving the image data and performing a compression procedure on the image data to generate a compression data according to the operation mode; a storage unit, coupled to the compression unit, for storing the compression data and the image data; a de-compression unit, coupled to the storage unit, for receiving the compression data and performing a de-compression procedure on the compression data to recover the image data according to the operation mode; and a display unit, for displaying the image data.

公开(公告)号：US20150042671A1

公开(公告)日：2015-02-12

申请号：US14078490

申请日：2013-11-12

Applicant: NOVATEK Microelectronics Corp.

Inventor： Kuei-Chung Chang ,  Feng-Jung Kuo ,  Hsi-Chi Ho

IPC: G06F1/32 ,  G06T1/60

CPC classification number: G06F1/3265 ,  G06T1/60 ,  G09G3/36 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2360/02 ,  Y02D10/153

Abstract: A data compression system for a liquid crystal display (LCD) includes a host and a drive circuit. The host is utilized for outputting image data in a first data format or a second data format according to an operation mode of the LCD. The drive circuit includes a bypass path, for transmitting the image data according to the operation mode; a compression unit, coupled to the host, for receiving the image data and performing a compression procedure on the image data to generate a compression data according to the operation mode; a storage unit, coupled to the compression unit, for storing the compression data and the image data; a de-compression unit, coupled to the storage unit, for receiving the compression data and performing a de-compression procedure on the compression data to recover the image data according to the operation mode; and a display unit, for displaying the image data.

Abstract translation: 液晶显示器（LCD）的数据压缩系统包括主机和驱动电路。 主机用于根据LCD的操作模式以第一数据格式或第二数据格式输出图像数据。 驱动电路包括旁路路径，用于根据操作模式发送图像数据; 耦合到主机的压缩单元，用于接收图像数据并对图像数据执行压缩过程以根据操作模式生成压缩数据; 耦合到压缩单元的存储单元，用于存储压缩数据和图像数据; 耦合到存储单元的解压缩单元，用于接收压缩数据并对压缩数据执行解压缩过程，以根据操作模式恢复图像数据; 以及显示单元，用于显示图像数据。

公开(公告)号：US20180314315A1

公开(公告)日：2018-11-01

申请号：US16021041

申请日：2018-06-28

Applicant: NOVATEK Microelectronics Corp.

Inventor： Kuei-Chung Chang ,  Feng-Jung Kuo ,  Hsi-Chi Ho

IPC: G06F1/32 ,  G06T1/60 ,  G09G3/36

CPC classification number: G06F1/3265 ,  G06T1/60 ,  G09G3/36 ,  G09G3/3611 ,  G09G2310/0245 ,  G09G2310/04 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2360/02 ,  Y02D10/153

Abstract: A drive circuit applicable to a display device includes a first signal path and a second signal path. The first signal path, configured to receive and transmit image data, includes a compression unit configured to perform a compression procedure on the image data to generate compression data; a storage unit configured to store the compression data; and a de-compression unit configured to perform a de-compression procedure on the compression data to recover the image data. The second signal path is configured to transmit the image data to the storage unit so as to bypass the compression unit, and transmit the image data received from the storage unit to a display unit so as to bypass the de-compression unit when the image data is not transmitted by the first signal path. The received image data is passed through the first signal path or the second signal path depending upon its characteristics.

公开(公告)号：US09001019B2

公开(公告)日：2015-04-07

申请号：US14197857

申请日：2014-03-05

Applicant: Novatek Microelectronics Corp.

Inventor： Yu-Hsun Peng ,  Hsi-Chi Ho ,  Li-Chun Huang

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G09G5/00 ,  G09G3/3688 ,  G09G2310/0289 ,  G09G2310/0297

Abstract: A data driver includes two data processing circuits for respectively providing positive and negative pixel voltages according to first and second pixel data, and a multiplexer circuit including multiplexer units. Each multiplexer unit has first and second input terminals respectively receiving the positive and negative pixel voltages, and an output terminal coupled to a data line. A first switching device has first and second switches serially coupled between the first input and output terminals. A node between the first and second switches is selectively grounded via a third switch. A second switching device has fourth and fifth switches serially coupled between the second input and output terminals. A node between the fourth and fifth switches is selectively grounded via a sixth switch. When the first and second switches turn on, the sixth switch turns on. When the fourth and fifth switches turn on, the third switch turns on.

Abstract translation: 数据驱动器包括用于分别根据第一和第二像素数据提供正和负像素电压的两个数据处理电路，以及包括多路复用器单元的多路复用器电路。 每个多路复用器单元具有分别接收正像素电压和负像素电压的第一和第二输入端子以及耦合到数据线的输出端子。 第一开关装置具有串联耦合在第一输入端和输出端之间的第一和第二开关。 第一和第二开关之间的节点经由第三开关选择性接地。 第二开关器件具有串联耦合在第二输入和输出端子之间的第四和第五开关。 第四开关和第五开关之间的节点通过第六开关选择性接地。 当第一和第二开关导通时，第六开关导通。 当第四和第五开关导通时，第三开关导通。

公开(公告)号：US08913049B2

公开(公告)日：2014-12-16

申请号：US13831971

申请日：2013-03-15

Applicant: Novatek Microelectronics Corp.

Inventor： Hsi-Chi Ho ,  Kuei-Chung Chang

IPC: G09G5/00 ,  H04N5/14 ,  G09G5/393

CPC classification number: G09G5/00 ,  G09G5/393 ,  G09G2320/106 ,  G09G2330/022 ,  G09G2360/10 ,  H04N5/14 ,  H04N5/144

Abstract: A motion detection method is adapted for an image display circuit including a motion detection circuit and an arbitration circuit. In this motion detection method, a number of motion quality observation windows are defined. Each motion quality observation window includes a start point and an ending point. In the motion quality observation windows, a write frame count value is adjusted according to a write frame command. At the end point of each motion quality observation window, if the write frame count value is equal to or bigger than a preset count value, an enable signal is outputted to the arbitration circuit to determine whether the image display circuit performs motion display. In the motion quality observation windows, the end point of the i-th motion quality observation window is located between the start point and the end point of the (i+1)-th motion quality observation window, where i is a positive integer.

Abstract translation: 运动检测方法适用于包括运动检测电路和仲裁电路的图像显示电路。 在该运动检测方法中，定义了多个运动质量观察窗口。 每个运动质量观察窗口包括起点和终点。 在运动质量观察窗口中，根据写入帧命令来调整写入帧计数值。 在每个运动质量观察窗口的终点处，如果写入帧计数值等于或大于预设计数值，则向仲裁电路输出使能信号，以确定图像显示电路是否执行运动显示。 在运动质量观察窗中，第i运动质量观察窗的终点位于第（i + 1）运动质量观察窗的起始点和终点之间，其中i是正整数。