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公开(公告)号：US12088198B2
公开(公告)日：2024-09-10
申请号：US17646481
申请日：2021-12-30
Applicant: NOVATEK Microelectronics Corp.
Inventor： Chieh-Ju Tsai , Ching-Jan Chen , Zhen-Guo Ding , Zhe-Hui Lin , Wei-Ling Chen
CPC classification number: H02M3/158 , H02M1/0025 , H02M3/157
Abstract: A power stage circuit generates an output signal according to an input signal and a control signal. A ramp generator circuit generates a ramp signal according to the control signal, the input signal, and the output signal. A calculation circuit generates a calculation signal according to the output signal and a reference signal. The calculation circuit operates in a first mode when the power converter operates in a light loading state, and the calculation circuit operates in a second mode when the power converter operates in a normal state. A control circuit generates the control signal according to the calculation signal and the ramp signal. The control circuit includes a comparator circuit and a control signal generator. The comparator circuit generates a comparison signal according to the calculation signal and the ramp signal. The control signal generator generates the control signal according to the comparison signal.
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Patent Agency Ranking
公开(公告)号：US12287689B2
公开(公告)日：2025-04-29
申请号：US18319047
申请日：2023-05-17
Applicant: NOVATEK MICROELECTRONICS CORP.
Inventor： Wei-Ling Chen
IPC: H02M1/00 , G06F1/3203
Abstract: An operation method of a power supply circuit which is provided with an input voltage to generate a positive output voltage and a negative output voltage is proposed. The power supply circuit includes five switches and is electrically connected with an inductor through a first inductor node and a second inductor node. The disclosed operation method includes determining the power supply circuit to operate in a mode, which includes three operation phases, a first, second and third phase. Energizing currents can be generated and provided both to enhance the positive output voltage and negative output voltage by employing the proposed operation method. Since there is no transition of the voltage level of the second inductor node during the second phase to third phase transition, it is believed that the present invention effectively achieves in suppressing redundant power switching loss and providing optimized output power efficiency.
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公开(公告)号：US20240333126A1
公开(公告)日：2024-10-03
申请号：US18193661
申请日：2023-03-31
Applicant: Novatek Microelectronics Corp.
Inventor： Zhe Hui Lin , Wei-Ling Chen , Lan-Shan Cheng
CPC classification number: H02M1/0025 , H02M3/158
Abstract: The invention provides a feedback control device and a feedback control method thereof. The feedback control device includes an enhancing circuit and a comparator. The enhancing circuit receives a feedback voltage corresponding to an output voltage of a DC-to-DC converter. In an embodiment, the enhancing circuit generates an enhanced feedback voltage based on the feedback voltage, and the comparator uses a comparison result between a reference voltage and the enhanced feedback voltage as a control signal to a feedback control terminal of the DC-to-DC converter. In another embodiment, the enhancing circuit generates an enhanced reference voltage based on the reference voltage, and the comparator uses a comparison result between the enhanced reference voltage and the feedback voltage as the control signal. In yet another embodiment, the comparator uses a comparison result between the enhanced reference voltage and the enhanced feedback voltage as the control signal.
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公开(公告)号：US11973425B2
公开(公告)日：2024-04-30
申请号：US17646478
申请日：2021-12-29
Applicant: NOVATEK Microelectronics Corp.
Inventor： Chieh-Ju Tsai , Ching-Jan Chen , Zhen-Guo Ding , Zhe-Hui Lin , Wei-Ling Chen
CPC classification number: H02M3/158 , H02M1/0025 , H02M3/157
Abstract: A power converter includes a power stage circuit, a ramp generator circuit, and a control circuit. The power stage circuit generates an output signal according to an input signal and a control signal. The ramp generator circuit generates a ramp signal according to the control signal, the input signal, and the output signal. The control circuit generates the control signal according to the output signal, a reference signal, and the ramp signal.
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公开(公告)号：US10148176B2
公开(公告)日：2018-12-04
申请号：US15391862
申请日：2016-12-28
Applicant: Novatek Microelectronics Corp.
Inventor： Wei-Ling Chen
Abstract: A DC-to-DC converter and a PWM device thereof are provided. The PWM device includes a ramp generator circuit, an error amplifier, a comparator and a clamping circuit. The error amplifier compares a voltage difference between the feedback voltage and the reference voltage to output a comparison voltage corresponding to the voltage difference. The comparator compares a ramp voltage of the ramp generator circuit and the comparison voltage of the error amplifier, so as to output a pulse signal. The clamping circuit determines whether to induce the comparison voltage to follow the ramp voltage. The clamping circuit is disabled when the PWM device is operated in the PWM mode, such that the comparison voltage and the ramp voltage are independent of each other. The clamping circuit is enabled when the PWM device is operated in the non-PWM mode, such that the comparison voltage follows the ramp voltage.
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公开(公告)号：US20180183331A1
公开(公告)日：2018-06-28
申请号：US15391862
申请日：2016-12-28
Applicant: Novatek Microelectronics Corp.
Inventor： Wei-Ling Chen
CPC classification number: H02M3/158 , H02M1/08 , H02M3/156 , H02M2001/0032 , H02M2001/009
Abstract: A DC-to-DC converter and a PWM device thereof are provided. The PWM device includes a ramp generator circuit, an error amplifier, a comparator and a clamping circuit. The error amplifier compares a voltage difference between the feedback voltage and the reference voltage to output a comparison voltage corresponding to the voltage difference. The comparator compares a ramp voltage of the ramp generator circuit and the comparison voltage of the error amplifier, so as to output a pulse signal. The clamping circuit determines whether to induce the comparison voltage to follow the ramp voltage. The clamping circuit is disabled when the PWM device is operated in the PWM mode, such that the comparison voltage and the ramp voltage are independent of each other. The clamping circuit is enabled when the PWM device is operated in the non-PWM mode, such that the comparison voltage follows the ramp voltage.
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