公开(公告)号：US09355211B2

公开(公告)日：2016-05-31

申请号：US14511283

申请日：2014-10-10

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Yibin Xia ,  Dinesh Rajasavari Amirtharaj ,  Ali Vahidsafa ,  Alan Smith ,  Senthilkumar Diraviam ,  Mohd Jamil Mohd

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06

Abstract: Systems, methods, and other embodiments associated with providing a unified tool for performing design constraints generation and verification for circuit designs are described. In one embodiment, the unified tool reads design data and design intent information for a circuit design. The unified tool generates physical flow elements and verification flow elements of the circuit design, together and in dependence on each other, based, at least in part, on the design data and the design intent information.

Abstract translation: 描述了与提供用于执行电路设计的设计约束生成和验证的统一工具相关联的系统，方法和其它实施例。 在一个实施例中，统一工具读取用于电路设计的设计数据和设计意图信息。 统一的工具至少部分地基于设计数据和设计意图信息，一起并相互依赖地生成电路设计的物理流程元素和验证流程元素。

公开(公告)号：US10275553B2

公开(公告)日：2019-04-30

申请号：US14155608

申请日：2014-01-15

Applicant: Oracle International Corporation

Inventor： Krishnan Sundaresan ,  Aravind Oommen ,  Mohd Jamil Mohd ,  Hemanga Lal Das ,  Pranjal Srivastava

IPC: G06F17/50

Abstract: A method for simulating a power consumption associated with a circuit. Once a netlist describing the circuit and an input stimulus for the netlist are obtained, the netlist is partitioned into multiple circuit blocks. Circuit logic models (CLMs) implemented in a hardware description language (HDL) are then obtained for the multiple circuit blocks and a logic netlist is generated from the multiple CLMs. A power vector for a CLM corresponding to a circuit block is calculated using a logic simulator inputting the logic netlist and the input stimulus. Further, a power consumption value is calculated for the circuit block using a circuit simulator and the power vector. The power consumption associated with the circuit is calculated based on the power consumption values for various circuit blocks.

公开(公告)号：US20150199460A1

公开(公告)日：2015-07-16

申请号：US14155608

申请日：2014-01-15

Applicant: Oracle International Corporation

Inventor： Krishnan Sundaresan ,  Aravind Oommen ,  Mohd Jamil Mohd ,  Hemanga Lal Das ,  Pranjal Srivastava

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: A method for simulating a power consumption associated with a circuit. The method includes: obtaining a netlist describing the circuit and an input stimulus for the netlist; partitioning the netlist into multiple circuit blocks; obtaining multiple circuit logic models (CLMs) implemented in a hardware description language (HDL) for the multiple circuit blocks; generating a logic netlist from the multiple CLMs; calculating, using a logic simulator inputting the logic netlist and the input stimulus, a power vector for a CLM corresponding to a first circuit block; calculating, using a circuit simulator and the power vector, a first power consumption value for the first circuit block; and calculating the power consumption associated with the circuit based on the first power consumption value.

Abstract translation: 一种用于模拟与电路相关联的功耗的方法。 该方法包括：获得描述电路的网表和网表的输入激励; 将网表划分成多个电路块; 获得用于多个电路块的硬件描述语言（HDL）中实现的多个电路逻辑模型（CLM）; 从多个CLM生成逻辑网表; 使用逻辑模拟器输入逻辑网表和输入激励来计算对应于第一电路块的CLM的功率矢量; 使用电路模拟器和功率矢量来计算第一电路块的第一功耗值; 以及基于所述第一功耗值计算与所述电路相关联的功耗。