公开(公告)号：US08751983B1

公开(公告)日：2014-06-10

申请号：US13789192

申请日：2013-03-07

Applicant: Oracle International Corporation

Inventor： Thomas Mitchell ,  Krishnan Sundaresan ,  Quan Tran ,  Yibin Xia

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A design partitioning method and apparatus includes an RTL reader module configured to receive, process, and parse hardware descriptive language of a circuit design; an expression graph module configured to trace identified signal dependencies to determine dependent elements along selected paths within the circuit design; a hierarchy flattener module configured to remove existing circuit design hierarchies based on the identified signal dependencies and determined dependent elements; a partition specification reader module that defines selected paths within the circuit design into a partition specification; a design partitioner module configured to separate the flattened circuit design hierarchy according to the partition specification; a re-partitioner module configured to create a second hierarchical circuit design structure based on the separated, flattened circuit design hierarchy that is behaviorally identical to the circuit design; and an RTL design write-out module configured to output the second hierarchical circuit design structure for analysis.

Abstract translation: 一种设计划分方法和装置，包括：RTL读取器模块，被配置为接收，处理和解析电路设计的硬件描述语言; 表示图模块，其被配置为跟踪所识别的信号依赖性以确定沿着所述电路设计内的选定路径的依赖元件; 层级平整器模块，被配置为基于所识别的信号依赖性和确定的依赖元素来去除现有的电路设计层级; 分区规范读取器模块，其将所述电路设计内的所选路径定义为分区规范; 设计分割器模块，被配置为根据分区规范分离扁平化的电路设计层级; 重新分割器模块，其被配置为基于与所述电路设计行为相同的分离的，扁平化的电路设计层级来创建第二分层电路设计结构; 以及被配置为输出用于分析的第二分层电路设计结构的RTL设计写出模块。

公开(公告)号：US09355211B2

公开(公告)日：2016-05-31

申请号：US14511283

申请日：2014-10-10

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Yibin Xia ,  Dinesh Rajasavari Amirtharaj ,  Ali Vahidsafa ,  Alan Smith ,  Senthilkumar Diraviam ,  Mohd Jamil Mohd

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06

Abstract: Systems, methods, and other embodiments associated with providing a unified tool for performing design constraints generation and verification for circuit designs are described. In one embodiment, the unified tool reads design data and design intent information for a circuit design. The unified tool generates physical flow elements and verification flow elements of the circuit design, together and in dependence on each other, based, at least in part, on the design data and the design intent information.

Abstract translation: 描述了与提供用于执行电路设计的设计约束生成和验证的统一工具相关联的系统，方法和其它实施例。 在一个实施例中，统一工具读取用于电路设计的设计数据和设计意图信息。 统一的工具至少部分地基于设计数据和设计意图信息，一起并相互依赖地生成电路设计的物理流程元素和验证流程元素。