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公开(公告)号：US10559418B2
公开(公告)日：2020-02-11
申请号：US15616266
申请日：2017-06-07
发明人： Chia-Ti Lai , Yung-Chi Chang , Ta-Wen Chang , Hsiao-Hua Chi , Lien-Hsing Chen
摘要： A method of assembling an inverter structure (1) includes: winding a coil set (12) around a bobbin (11), the bobbin (11) including a first side (11a) and a second side (11b) opposite to each other; inserting a first core pillar (21) of a first iron core (20) into a through hole (110) of the bobbin (11); sequentially placing a first insulation body (30), a middle iron core (40) and a second insulation body (50) into the through hole (110) from a second side (11b) of the bobbin (11); and inserting a second core pillar (61) of a second iron core (60) into the through hole (110) from the second side (11b) of the bobbin (11) and arranging the second core pillar (61) to be in contact with the second insulation body (50).
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公开(公告)号：US12015350B2
公开(公告)日：2024-06-18
申请号：US17872834
申请日：2022-07-25
发明人： Lien-Hsing Chen , Ta-Wen Chang , Hsiao-Hua Chi , Ching-Ming Lai , Wei-Hsuan Lin
CPC分类号： H02M3/1586 , H02M1/0043
摘要： A novel power supply apparatus (10) includes a microcontroller (102) and a plurality of voltage converters (104). If the voltage converters (104) are in a boost mode and a plurality of duty cycles of the voltage converters (104) calculated by the microcontroller (102) are less than 0.5, the microcontroller (102) is configured to limit at least one of the duty cycles of the voltage converters (104) to 0.5. If the voltage converters (104) are in a buck mode and the duty cycles of the voltage converters (104) calculated by the microcontroller (102) are greater than 0.5, the microcontroller (102) is configured to limit at least one of the duty cycles of the voltage converters (104) to 0.5.
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3.发明授权公开(公告)号：US11705909B1
公开(公告)日：2023-07-18
申请号：US17813926
申请日：2022-07-20
发明人： Tien-Yu Chen , Liang-Jhou Dai , Wei-Sheng Wang , Hsiao-Hua Chi , Lien-Hsing Chen
IPC分类号： H03L7/08
CPC分类号： H03L7/08
摘要： A frequency-locked circuit for a variable frequency topology is configured to trigger a Pulse Width Modulation (PWM) controller to lock a frequency of a driving signal outputted by the PWM controller. The frequency-locked circuit includes an AC wave generating circuit and a comparator. The AC wave generating circuit receives and converts the driving signal to generate an AC wave signal. The comparator is electrically connected to the AC wave generating circuit and receives the AC wave signal. The comparator compares the AC wave signal with a reference signal to generate a comparison output signal. In response to determining that the AC wave signal is greater than the reference signal, the comparison output signal triggers the PWM controller to convert the driving signal from one voltage level to another voltage level so as to lock the frequency. The one voltage level is different from the another voltage level.
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