公开(公告)号：US07353485B1

公开(公告)日：2008-04-01

申请号：US11200627

申请日：2005-08-10

申请人： Parivallal Kannan ,  Victor Z. Slonim ,  Salim Abid

发明人： Parivallal Kannan ,  Victor Z. Slonim ,  Salim Abid

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5072 ,  G06F2217/62

摘要： A method of global clock placement for a circuit design to be implemented on a programmable logic device (PLD) can include identifying clock properties for the circuit design and identifying physical clock region attributes for the PLD. The method further can include specifying an Integer Linear Programming formulation (ILP) of a clock placement problem for the circuit design from the clock properties and the physical clock region attributes. The ILP formulation can be solved to determine whether a feasible clock placement exists for the circuit design.

摘要翻译： 要在可编程逻辑器件（PLD）上实现的电路设计的全局时钟放置方法可以包括识别电路设计的时钟属性并识别PLD的物理时钟区域属性。 该方法还可以包括根据时钟属性和物理时钟区域属性指定用于电路设计的时钟布置问题的整数线性规划公式（ILP）。 可以解决ILP公式，以确定电路设计中是否存在可行的时钟布局。

公开(公告)号：US07480884B1

公开(公告)日：2009-01-20

申请号：US11501155

申请日：2006-08-08

申请人： Victor Z. Slonim ,  Parivallal Kannan ,  Salim Abid

发明人： Victor Z. Slonim ,  Parivallal Kannan ,  Salim Abid

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/08

摘要： A method of assigning input/output (I/O) objects of a circuit design to banks of a target device using integer linear programming can include assigning the I/O objects of the circuit design to I/O groups according to compatibility among the I/O objects, and establishing a plurality of relationships, comprising measures of bank capacity, regulating assignment of the I/O objects of I/O groups to banks of the target device. Each measure of bank capacity can indicate a maximum number of I/O objects from a selected I/O group that can be assigned to a selected bank of the target device. The method also can include determining whether a feasible solution exists for assignment of the I/O objects of the circuit design to banks of the target device by minimizing an object function while observing the plurality of relationships.

摘要翻译： 使用整数线性规划将电路设计的输入/输出（I / O）对象分配给目标设备的组的方法可以包括根据I中的兼容性将电路设计的I / O对象分配给I / O组 / O对象，以及建立多个关系，包括银行容量的度量，调整I / O组的I / O对象对目标设备的存储体的分配。 每个银行容量的度量可以指示可以分配给目标设备的选定库的所选I / O组的最大数量的I / O对象。 该方法还可以包括通过在观察多个关系的同时最小化对象功能来确定是否存在用于将电路设计的I / O对象分配给目标设备的存储体的可行解决方案。

公开(公告)号：US07451422B1

公开(公告)日：2008-11-11

申请号：US11500524

申请日：2006-08-08

申请人： Victor Z. Slonim ,  Parivallal Kannan ,  Salim Abid

发明人： Victor Z. Slonim ,  Parivallal Kannan ,  Salim Abid

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5036 ,  G06F17/5072 ,  G06F2217/08

摘要： A method of assigning I/O objects to banks of a target device can include concurrently assigning I/O objects, including select I/O objects and clock I/O objects, of the circuit design to I/O groups according to an I/O standard associated with each I/O object. Each I/O group can include only I/O objects of a same I/O standard. The method also can include establishing a plurality of linear constraints for regulating assignment of the I/O groups to banks of the target device. The linear constraints can include range constraints indicating I/O banks capable of hosting clock I/O objects. The method also can include defining mutual relationships among selected ones of the linear constraints. An indication as to whether a feasible solution exists for assignment of the I/O groups to banks of the target device can be provided by minimizing a linear objective function while observing the linear constraints and the mutual relationships.

摘要翻译： 将I / O对象分配给目标设备的银行的方法可以包括根据I / O组向I / O组同时分配电路设计的I / O对象，包括I / O对象和时钟I / O对象， O标准与每个I / O对象相关联。 每个I / O组只能包含相同I / O标准的I / O对象。 该方法还可以包括建立多个线性约束，用于调节I / O组对目标设备的组的分配。 线性约束可以包括指示能承载时钟I / O对象的I / O组的范围约束。 该方法还可以包括定义线性约束的选定线之间的相互关系。 可以通过在观察线性约束和相互关系的同时最小化线性目标函数来提供是否存在用于将I / O组分配给目标设备的银行的可行解决方案的指示。

公开(公告)号：US07299439B1

公开(公告)日：2007-11-20

申请号：US11135980

申请日：2005-05-24

申请人： Victor Z. Slonim ,  Salim Abid

发明人： Victor Z. Slonim ,  Salim Abid

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method of input/output (I/O) assignment for a circuit design for a programmable logic device (PLD) can include determining I/O types for I/O objects specified by the circuit design, defining a plurality of virtual I/O bank-groups, wherein each virtual I/O bank-group includes at least one virtual I/O bank, and binding I/O objects of the circuit design into I/O groups according to the I/O types. A binary compatibility matrix can be created. The binary compatibility matrix can indicate the compatibility between the virtual I/O bank-groups and the I/O groups based upon the I/O types of I/O objects within each I/O group. A determination can be made as to whether a feasible solution exists for I/O assignment of the I/O objects of the circuit design according to a plurality of constraints and the binary compatibility matrix.

摘要翻译： 用于可编程逻辑器件（PLD）的电路设计的输入/输出（I / O）分配的方法可以包括确定由电路设计指定的I / O对象的I / O类型，定义多个虚拟I / O 银行组，其中每个虚拟I / O组组包括至少一个虚拟I / O组，并且根据I / O类型将电路设计的I / O对象绑定到I / O组中。 可以创建二进制兼容性矩阵。 二进制兼容性矩阵可以基于每个I / O组内的I / O对象的I / O类型来指示虚拟I / O组组与I / O组之间的兼容性。 可以确定根据多个约束和二进制兼容性矩阵是否存在针对电路设计的I / O对象的I / O分配的可行解决方案。

公开(公告)号：US07194722B1

公开(公告)日：2007-03-20

申请号：US11009260

申请日：2004-12-09

申请人： Salim Abid ,  Victor Z. Slonim

发明人： Salim Abid ,  Victor Z. Slonim

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5068 ,  G06F2217/08

摘要： A method of physical design for a programmable logic device can include associating target locations for movable objects with criticality measures and calculating the criticality measure for each target location. A probability for each target location can be calculated. The probability of the target location can be dependent upon the criticality measure for that target location. The method further can include selecting a target location for one of the movable objects for controlled movement during a simulated annealing process. The target location can be selected according to the probability corresponding to each target location.

摘要翻译： 可编程逻辑器件的物理设计方法可以包括将可移动对象的目标位置与关键性度量相关联并且计算每个目标位置的临界度度量。 可以计算每个目标位置的概率。 目标位置的概率可以取决于该目标位置的临界度度量。 该方法还可以包括在模拟退火过程期间选择可移动物体中的一个用于受控移动的目标位置。 可以根据与每个目标位置对应的概率来选择目标位置。

公开(公告)号：US07194721B1

公开(公告)日：2007-03-20

申请号：US10868956

申请日：2004-06-15

申请人： Victor Z. Slonim ,  Salim Abid

发明人： Victor Z. Slonim ,  Salim Abid

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of physical design for a programmable logic device (PLD) can include associating movable objects of the PLD with a criticality measure that is dependent upon timing information for a configuration of the PLD (115). The method further can include calculating the criticality measure for each movable object (125) and calculating a probability for each movable object (130). The probability can depend upon the criticality measure for the movable object. The method also can include selecting one or more of the movable objects for controlled move generation within a simulated annealing process (135). Movable objects are selected for controlled move generation according to the probabilities assigned to the movable objects.

摘要翻译： 可编程逻辑器件（PLD）的物理设计方法可以包括将PLD的可移动对象与依赖于PLD（115）的配置的定时信息的关键性度量相关联。 该方法还可以包括计算每个可移动对象（125）的关键度测量并计算每个可移动对象（130）的概率。 概率可以取决于可移动物体的临界度测量。 该方法还可以包括在模拟退火过程（135）内选择用于受控移动生成的一个或多个可移动对象。 可移动物体根据分配给可移动物体的概率被选择用于受控移动生成。

公开(公告)号：US06760899B1

公开(公告)日：2004-07-06

申请号：US10215978

申请日：2002-08-08

申请人： Jay T. Young ,  Salim Abid

发明人： Jay T. Young ,  Salim Abid

IPC分类号： G06F1750

CPC分类号： G06F17/5072

摘要： Method and code for dedicated resource placement enhancement is described. More particularly, a local area of a network is obtained for determining placement options of logic blocks to increase availability of dedicated resources within the local area. Each placement option is scored. This scoring may be based in part on whether a signal is to be propagated over a dedicated resource, and whether this signal is presently meeting a slack or target delay. Logic blocks, and therefore the dedicated resources, are placed after scoring.

摘要翻译： 描述了专用资源放置增强的方法和代码。 更具体地，获得网络的局部区域以确定逻辑块的布局选项以增加局部区域内的专用资源的可用性。 每个展示位置选项都得分。 该评分可部分地基于信号是否通过专用资源传播，以及该信号是否正在满足松弛或目标延迟。 逻辑块，因此专用的资源，被放置在得分后。

公开(公告)号：US07137090B1

公开(公告)日：2006-11-14

申请号：US10637733

申请日：2003-08-08

申请人： Walter A. Manaker, Jr. ,  Salim Abid

发明人： Walter A. Manaker, Jr. ,  Salim Abid

IPC分类号： G06F17/50 ,  G06F9/45 ,  H03K19/00

CPC分类号： G06F17/5031 ,  G06F17/5068

摘要： Method and apparatus for phase-timing compensation is described. More particularly, a clock source and a clock sink of a path are identified for phase-timing compensation for a design. An absolute path slack is obtained, and phase offset of the clock source relative to the clock sink is determined. A normalizing factor responsive to the phase offset is generated. A normalized slack is computed using the absolute path slack and the normalizing factor.

摘要翻译： 描述了相位定时补偿的方法和装置。 更具体地，识别路径的时钟源和时钟信宿用于设计的相位定时补偿。 获得绝对路径松弛，并确定时钟源相对于时钟接收器的相位偏移。 产生响应相位偏移的归一化因子。 使用绝对路径松弛和归一化因子来计算归一化松弛。